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add core-v-x-if #1

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merged 14 commits into from
Oct 5, 2023
Merged

add core-v-x-if #1

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35df016
manually adapted https://github.com/esl-epfl/cv32e40px/commit/3e41039…
davideschiavone Jul 19, 2023
203b667
manually adapted 9f03a9321b7373799674940bb8ef2a5fd1bfb759
davideschiavone Jul 19, 2023
6a7ce2c
update cadence lec
davideschiavone Jul 20, 2023
75df747
renaming files to cv32e40px
davideschiavone Jul 20, 2023
54e154c
replaced cv32e40p with cv32e40px in module names
davideschiavone Jul 20, 2023
fed0713
update top file
davideschiavone Jul 20, 2023
21a6626
fix undriven signals
davideschiavone Jul 20, 2023
bfb6b76
format verible
davideschiavone Jul 20, 2023
ddfa8cc
merge master
davideschiavone Oct 4, 2023
e0f5816
fix undriven signal
davideschiavone Oct 4, 2023
326891e
remove unused signals
davideschiavone Oct 4, 2023
28ddffa
update to newer spec
davideschiavone Oct 5, 2023
d81cd5c
fix parameter in if_stage
davideschiavone Oct 5, 2023
2c4204d
fix verible
davideschiavone Oct 5, 2023
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527 changes: 0 additions & 527 deletions bhv/cv32e40p_tb_wrapper.sv
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8 changes: 4 additions & 4 deletions bhv/cv32e40p_apu_tracer.sv → bhv/cv32e40px_apu_tracer.sv
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Expand Up @@ -21,7 +21,7 @@
////////////////////////////////////////////////////////////////////////////////
// Engineer: Arjan Bink - arjan.bink@silabs.com //
// //
// Design Name: cv32e40p_apu_tracer.sv (APU trace) //
// Design Name: cv32e40px_apu_tracer.sv (APU trace) //
// Project Name: CV32E40P //
// Language: SystemVerilog //
// //
Expand All @@ -30,14 +30,14 @@
// - APU register file write address //
// - APU register file write data //
// //
// Note: This code was here from cv32e40p_core.sv in order to //
// Note: This code was here from cv32e40px_core.sv in order to //
// remove the use of global defines in the RTL code. //
// //
////////////////////////////////////////////////////////////////////////////////

`ifdef CV32E40P_APU_TRACE

module cv32e40p_apu_tracer (
module cv32e40px_apu_tracer (
input logic clk_i,
input logic rst_n,
input logic [31:0] hart_id_i,
Expand Down Expand Up @@ -74,6 +74,6 @@ module cv32e40p_apu_tracer (
$fclose(apu_trace);
end

endmodule // cv32e40p_apu_tracer
endmodule // cv32e40px_apu_tracer

`endif // CV32E40P_APU_TRACE
12 changes: 6 additions & 6 deletions bhv/cv32e40p_core_log.sv → bhv/cv32e40px_core_log.sv
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Expand Up @@ -21,7 +21,7 @@
////////////////////////////////////////////////////////////////////////////////
// Engineer: Arjan Bink - arjan.bink@silabs.com //
// //
// Design Name: cv32e40p_core_log.sv (cv32e40p_core simulation log) //
// Design Name: cv32e40px_core_log.sv (cv32e40px_core simulation log) //
// Project Name: CV32E40P //
// Language: SystemVerilog //
// //
Expand All @@ -30,13 +30,13 @@
// - top level parameter settings //
// - illegal instructions //
// //
// Note: This code was here from cv32e40p_core.sv and //
// cv32e40p_controller.sv in order to remove the use of //
// Note: This code was here from cv32e40px_core.sv and //
// cv32e40px_controller.sv in order to remove the use of //
// global defines in the RTL code. //
// //
////////////////////////////////////////////////////////////////////////////////

module cv32e40p_core_log #(
module cv32e40px_core_log #(
parameter COREV_PULP = 1, // PULP ISA Extension (incl. custom CSRs and hardware loop, excl. cv.elw)
parameter COREV_CLUSTER = 0, // PULP Cluster interface (incl. cv.elw)
parameter FPU = 0, // Floating Point Unit (interfaced via APU interface)
Expand All @@ -53,7 +53,7 @@ module cv32e40p_core_log #(
// Log top level parameter values
initial begin
$display(
"[cv32e40p_core]: COREV_PULP = %d, COREV_CLUSTER = %d, FPU %d, ZFINX %d, NUM_MHPMCOUNTERS %d",
"[cv32e40px_core]: COREV_PULP = %d, COREV_CLUSTER = %d, FPU %d, ZFINX %d, NUM_MHPMCOUNTERS %d",
COREV_PULP, COREV_CLUSTER, FPU, ZFINX, NUM_MHPMCOUNTERS);
end

Expand All @@ -65,4 +65,4 @@ module cv32e40p_core_log #(
end
end

endmodule // cv32e40p_core_log
endmodule // cv32e40px_core_log
0 bhv/cv32e40p_instr_trace.svh → bhv/cv32e40px_instr_trace.svh
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File renamed without changes.
10 changes: 5 additions & 5 deletions bhv/cv32e40p_rvfi.sv → bhv/cv32e40px_rvfi.sv
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Expand Up @@ -20,11 +20,11 @@
// Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>
// Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>

`include "cv32e40p_rvfi_pkg.sv"
`include "cv32e40px_rvfi_pkg.sv"

module cv32e40p_rvfi
import cv32e40p_pkg::*;
import cv32e40p_rvfi_pkg::*;
module cv32e40px_rvfi
import cv32e40px_pkg::*;
import cv32e40px_rvfi_pkg::*;
#(
parameter FPU = 0,
parameter ZFINX = 0
Expand Down Expand Up @@ -1823,4 +1823,4 @@ insn_trace_t trace_if, trace_id, trace_ex, trace_ex_next, trace_wb;
join
end

endmodule // cv32e40p_rvfi
endmodule // cv32e40px_rvfi
10 changes: 5 additions & 5 deletions bhv/cv32e40p_rvfi_trace.sv → bhv/cv32e40px_rvfi_trace.sv
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Expand Up @@ -19,8 +19,8 @@
// Contributors: Halfdan Bechmann, Silicon Labs <halfdan.bechmann@silabs.com>
// Yoann Pruvost, Dolphin Design <yoann.pruvost@dolphin.fr>

module cv32e40p_rvfi_trace
import cv32e40p_pkg::*;
module cv32e40px_rvfi_trace
import cv32e40px_pkg::*;
#(
parameter FPU = 0,
parameter ZFINX = 0
Expand Down Expand Up @@ -67,7 +67,7 @@ module cv32e40p_rvfi_trace
input logic [31:0] rvfi_mem_wdata
);

import cv32e40p_tracer_pkg::*;
import cv32e40px_tracer_pkg::*;

logic rst_n;
assign rst_n = rst_ni;
Expand Down Expand Up @@ -153,15 +153,15 @@ module cv32e40p_rvfi_trace
assign imm_shuffle_type = '0;
assign imm_clip_type = '0;

cv32e40p_compressed_decoder #(
cv32e40px_compressed_decoder #(
.FPU(FPU)
) rvfi_trace_decompress_i (
.instr_i(rvfi_insn),
.instr_o(decomp_insn),
.is_compressed_o(is_compressed)
);

`include "cv32e40p_instr_trace.svh"
`include "cv32e40px_instr_trace.svh"
instr_trace_t trace_retire;

function instr_trace_t trace_new_instr();
Expand Down
6 changes: 3 additions & 3 deletions bhv/cv32e40p_sim_clock_gate.sv → bhv/cv32e40px_sim_clock_gate.sv
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Expand Up @@ -8,11 +8,11 @@
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.

// !!! cv32e40p_sim_clock_gate file is meant for simulation only !!!
// !!! cv32e40px_sim_clock_gate file is meant for simulation only !!!
// !!! It must not be used for ASIC synthesis !!!
// !!! It must not be used for FPGA synthesis !!!

module cv32e40p_clock_gate (
module cv32e40px_clock_gate (
input logic clk_i,
input logic en_i,
input logic scan_cg_en_i,
Expand All @@ -27,4 +27,4 @@ module cv32e40p_clock_gate (

assign clk_o = clk_i & clk_en;

endmodule // cv32e40p_clock_gate
endmodule // cv32e40px_clock_gate
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