update to newer spec

rtl/cv32e40px_id_stage.sv

@@ -1015,7 +1015,7 @@ module cv32e40px_id_stage
   logic [1:0] x_mem_data_type_id;
 
   generate
-    if (COREV_X_IF) begin : gen_x_disp
+    if (COREV_X_IF != 0) begin : gen_x_disp
       ////////////////////////////////////////
       //  __  __     ____ ___ ____  ____    //
       //  \ \/ /    |  _ \_ _/ ___||  _ \   //
@@ -1138,13 +1138,13 @@ module cv32e40px_id_stage
       always_comb begin
         x_mem_data_type_id = 2'b00;
         case (x_mem_req_i.size)
-          2'b00: x_mem_data_type_id = 2'b10;  // SB
-          2'b01: x_mem_data_type_id = 2'b01;  // SH
-          2'b10: x_mem_data_type_id = 2'b00;  // SW
+          3'd0: x_mem_data_type_id = 2'b10;  // SB
+          3'd1: x_mem_data_type_id = 2'b01;  // SH
+          3'd2: x_mem_data_type_id = 2'b00;  // SW
+          default: x_mem_data_type_id = 2'b00;  // SW
         endcase
       end
 
-
     end else begin : gen_no_x_disp
 
       // default illegal instruction assignment

rtl/cv32e40px_x_disp.sv

@@ -98,7 +98,7 @@ module cv32e40px_x_disp
   // scoreboard, id and satus signals
   logic [31:0] scoreboard_q, scoreboard_d;
   logic [3:0] id_q, id_d;
-  logic [3:0] instr_offloaded_q, instr_offloaded_d;
+  logic instr_offloaded_q, instr_offloaded_d;
   logic [3:0] mem_counter_q, mem_counter_d;
   logic dep;
   logic outstanding_mem;
@@ -182,7 +182,7 @@ module cv32e40px_x_disp
   always_comb begin
     scoreboard_d = scoreboard_q;
     if (x_issue_resp_writeback_i & x_issue_valid_o & x_issue_ready_i
-        & ~((waddr_id_i == x_result_rd_i) & x_result_valid_i & x_result_rd_i)) begin
+        & ~((waddr_id_i == x_result_rd_i) & x_result_valid_i & (x_result_rd_i != '0))) begin
       scoreboard_d[waddr_id_i] = 1'b1;
     end
     if (x_result_valid_i & x_result_we_i) begin

rtl/include/cv32e40px_core_v_xif_pkg.sv

@@ -22,75 +22,81 @@ package cv32e40px_core_v_xif_pkg;
   parameter logic [31:0] X_MISA = '0;
   parameter logic [1:0] X_ECS_XS = '0;
 
-  // interface structs
+  localparam int XLEN = 32;
+
   typedef struct packed {
-    logic [15:0] instr;
-    logic [1:0] mode;
-    logic [X_ID_WIDTH-1:0] id;
+    logic [          15:0] instr; // Offloaded compressed instruction
+    logic [           1:0] mode;  // Privilege level
+    logic [X_ID_WIDTH-1:0] id;    // Identification number of the offloaded compressed instruction
   } x_compressed_req_t;
 
   typedef struct packed {
-    logic [31:0] instr;
-    logic accept;
+    logic [31:0] instr;   // Uncompressed instruction
+    logic        accept;  // Is the offloaded compressed instruction (id) accepted by the coprocessor?
   } x_compressed_resp_t;
 
   typedef struct packed {
-    logic [31:0] instr;
-    logic [1:0] mode;
-    logic [X_ID_WIDTH-1:0] id;
-    logic [X_NUM_RS-1:0][X_RFR_WIDTH-1:0] rs;
-    logic [X_NUM_RS-1:0] rs_valid;
-    logic [5:0] ecs;
-    logic ecs_valid;
+    logic [          31:0]                  instr;     // Offloaded instruction
+    logic [           1:0]                  mode;      // Privilege level
+    logic [X_ID_WIDTH-1:0]                  id;        // Identification of the offloaded instruction
+    logic [X_NUM_RS  -1:0][X_RFR_WIDTH-1:0] rs;        // Register file source operands for the offloaded instruction
+    logic [X_NUM_RS  -1:0]                  rs_valid;  // Validity of the register file source operand(s)
+    logic [           5:0]                  ecs;       // Extension Context Status ({mstatus.xs, mstatus.fs, mstatus.vs})
+    logic                                   ecs_valid; // Validity of the Extension Context Status
   } x_issue_req_t;
 
   typedef struct packed {
-    logic accept;
-    logic writeback;
-    //logic float;
-    logic dualwrite;
-    logic dualread;
-    logic loadstore;
-    logic exc;
+    logic       accept;     // Is the offloaded instruction (id) accepted by the coprocessor?
+    logic       writeback;  // Will the coprocessor perform a writeback in the core to rd?
+    logic       dualwrite;  // Will the coprocessor perform a dual writeback in the core to rd and rd+1?
+    logic [2:0] dualread;   // Will the coprocessor require dual reads from rs1\rs2\rs3 and rs1+1\rs2+1\rs3+1?
+    logic       loadstore;  // Is the offloaded instruction a load/store instruction?
+    logic       ecswrite ;  // Will the coprocessor write the Extension Context Status in mstatus?
+    logic       exc;        // Can the offloaded instruction possibly cause a synchronous exception in the coprocessor itself?
   } x_issue_resp_t;
 
   typedef struct packed {
-    logic [X_ID_WIDTH-1:0] id;
-    logic commit_kill;
+    logic [X_ID_WIDTH-1:0] id;          // Identification of the offloaded instruction
+    logic                  commit_kill; // Shall an offloaded instruction be killed?
   } x_commit_t;
 
   typedef struct packed {
-    logic [X_ID_WIDTH-1:0] id;
-    logic [31:0] addr;
-    logic [1:0] mode;
-    logic [1:0] size;
-    logic we;
-    logic [X_MEM_WIDTH-1:0] wdata;
-    logic last;
-    logic spec;
+    logic [X_ID_WIDTH   -1:0] id;    // Identification of the offloaded instruction
+    logic [             31:0] addr;  // Virtual address of the memory transaction
+    logic [              1:0] mode;  // Privilege level
+    logic                     we;    // Write enable of the memory transaction
+    logic [              2:0] size;  // Size of the memory transaction
+    logic [X_MEM_WIDTH/8-1:0] be;    // Byte enables for memory transaction
+    logic [              1:0] attr;  // Memory transaction attributes
+    logic [X_MEM_WIDTH  -1:0] wdata; // Write data of a store memory transaction
+    logic                     last;  // Is this the last memory transaction for the offloaded instruction?
+    logic                     spec;  // Is the memory transaction speculative?
   } x_mem_req_t;
 
   typedef struct packed {
-    logic exc;
-    logic [5:0] exccode;
-    logic dbg;
+    logic       exc;      // Did the memory request cause a synchronous exception?
+    logic [5:0] exccode;  // Exception code
+    logic       dbg;      // Did the memory request cause a debug trigger match with ``mcontrol.timing`` = 0?
   } x_mem_resp_t;
 
   typedef struct packed {
-    logic [X_ID_WIDTH-1:0] id;
-    logic [X_MEM_WIDTH-1:0] rdata;
-    logic err;
-    logic dbg;
+    logic [X_ID_WIDTH -1:0] id;     // Identification of the offloaded instruction
+    logic [X_MEM_WIDTH-1:0] rdata;  // Read data of a read memory transaction
+    logic                   err;    // Did the instruction cause a bus error?
+    logic                   dbg;    // Did the read data cause a debug trigger match with ``mcontrol.timing`` = 0?
   } x_mem_result_t;
 
   typedef struct packed {
-    logic [X_ID_WIDTH-1:0] id;
-    logic [X_RFW_WIDTH-1:0] data;
-    logic [4:0] rd;
-    logic we;
-    logic [2:0] ecswe;
-    logic [5:0] ecsdata;
-    logic exc;
-    logic [5:0] exccode;
+    logic [X_ID_WIDTH      -1:0] id;      // Identification of the offloaded instruction
+    logic [X_RFW_WIDTH     -1:0] data;    // Register file write data value(s)
+    logic [                 4:0] rd;      // Register file destination address(es)
+    logic [X_RFW_WIDTH/XLEN-1:0] we;      // Register file write enable(s)
+    logic [                 5:0] ecsdata; // Write data value for {mstatus.xs, mstatus.fs, mstatus.vs}
+    logic [                 2:0] ecswe;   // Write enables for {mstatus.xs, mstatus.fs, mstatus.vs}
+    logic                        exc;     // Did the instruction cause a synchronous exception?
+    logic [                 5:0] exccode; // Exception code
+    logic                        err;     // Did the instruction cause a bus error?
+    logic                        dbg;     // Did the instruction cause a debug trigger match with ``mcontrol.timing`` = 0?
   } x_result_t;
+
 endpackage