Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

build/efinix: added argument to change synthesis options configurations #2009

Merged
merged 1 commit into from
Jul 8, 2024

Conversation

trabucayre
Copy link
Collaborator

As mentioned in #1971, synthesis options like --mode may be adapted/configured at build time instead of hardcoded.

Solution proposed in #1971 imply to modify target and/or platform to set these options.

This PR address this issue by adding arguments to configure efx_map at build time.

Note: add efx_map aren't updated to use argument approach and it may make sense to have the same thing, at least, efx_pgm.

@enjoy-digital enjoy-digital merged commit 7de4f01 into enjoy-digital:master Jul 8, 2024
1 check passed
@enjoy-digital
Copy link
Owner

Thanks @trabucayre!

@AndrewD
Copy link
Collaborator

AndrewD commented Jul 9, 2024

@trabucayre @enjoy-digital this doesn't build. There are typos (patch below) but with that fixed the build fails when calling the script. I reverted this change to have master work with efinity.

diff --git a/litex/build/efinix/efinity.py b/litex/build/efinix/efinity.py
index 5322536b3..20485013f 100644
--- a/litex/build/efinix/efinity.py
+++ b/litex/build/efinix/efinity.py
@@ -317,12 +317,12 @@ class EfinityToolchain(GenericToolchain):
             "--infer-clk-enable",           self._infer_clk_enable,
             "--infer-sync-set-reset",       "1",
             "--fanout-limit",               "0",
-            "--bram_output_regs_packing",   self._bram_output_regs_packaging,
+            "--bram_output_regs_packing",   self._bram_output_regs_packing,
             "--retiming",                   self._retiming,
             "--seq_opt",                    self._seq_opt,
             "--blast_const_operand_adders", "1",
-            "--mult_input_regs_packing",    self._mult_input_regs_packaging,
-            "--mult_output_regs_packing",   self._mult_output_regs_packaing,
+            "--mult_input_regs_packing",    self._mult_input_regs_packing,
+            "--mult_output_regs_packing",   self._mult_output_regs_packing,
             "--veri_option",                "verilog_mode=verilog_2k,vhdl_mode=vhdl_2008",
             "--work-dir",                   "work_syn",
             "--output-dir",                 "outflow",

@enjoy-digital
Copy link
Owner

Thanks @AndrewD for the feedback, we'll fix today.

@enjoy-digital
Copy link
Owner

@AndrewD: This should be good with 549d23e, will do more test later today.

@AndrewD
Copy link
Collaborator

AndrewD commented Jul 9, 2024

Thanks @enjoy-digital - that builds again for us.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

3 participants