Add support for the CV32E41P RISC-V CPU

[pcotret]

Worked in simulation and on a board (Nexys4-DDR). Mostly inspired by the CV32E40P PR #535

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb 14 2022 22:39:52
 BIOS CRC passed (3f045d30)

 Migen git sha1: ac70301
 LiteX git sha1: d506b441

--=============== SoC ==================--
CPU:		CV32E41P @ 1MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128KiB
SRAM:		8KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_list
Available memory regions:
ROM       0x00000000 0x20000 
SRAM      0x01000000 0x2000 
CSR       0x82000000 0x10000 

Regarding interrupts and my previous issue (#1200), may I ask for a quick review?
It works, but it may not be the most elegant solution.

In order to help, I wrote some notes about how interrupt signals are implemented in the CV32E41P compared to the (old) CV32E40P:
https://gist.github.com/pcotret/855279aa18393c14345095f2e7a6a99f

[enjoy-digital]

Thanks @pcotret! This looks good and is perfectly fine for an initial support. We can merge it now and I'll try to do a closer review of the interrupt support soon.