interconnect/axi/axi_lite: Add bursting property even if always False.

litex/soc/interconnect/axi/axi_lite.py

@@ -57,6 +57,7 @@ def __init__(self, data_width=32, address_width=32, addressing="byte", clock_dom
         # -----------
         self.data_width    = data_width
         self.address_width = address_width
+        self.bursting      = bursting
         self.addressing    = addressing
         self.clock_domain  = clock_domain