soc/add_ethernet: Add 64-bit data_width support.

enjoy-digital · Jun 27, 2024 · 9c07b45 · 9c07b45
1 parent 3dd3477
commit 9c07b45
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
@@ -1850,14 +1850,14 @@ def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False,
         from liteeth.phy.model import LiteEthPHYModel
 
         # MAC.
-        assert data_width in [8, 32]
+        assert data_width in [8, 32, 64]
         with_sys_datapath = (data_width == 32)
         self.check_if_exists(name)
         if with_timestamp:
             self.timer0.add_uptime()
         ethmac = LiteEthMAC(
             phy        = phy,
-            dw         = 32,
+            dw         = {8: 32, 32: 32, 64: 64}[data_width],
             interface  = "wishbone",
             endianness = self.cpu.endianness,
             nrxslots   = nrxslots, rxslots_read_only  = rxslots_read_only,