core: Switch to LiteX's Reduce.

litejesd204b/core.py

@@ -5,14 +5,13 @@
 # Copyright (c) 2016 Robert Jordens <jordens@gmail.com>
 # SPDX-License-Identifier: BSD-2-Clause
 
-from functools import reduce
-from operator import and_
-
 from migen import *
 from migen.genlib.cdc import MultiReg, ElasticBuffer
 from migen.genlib.misc import WaitTimer
 from migen.genlib.fifo import SyncFIFO
 
+from litex.gen import *
+
 from litex.build.io import DifferentialInput, DifferentialOutput
 
 from litex.soc.interconnect.csr import *
@@ -193,7 +192,7 @@ def __init__(self, phys, jesd_settings, converter_data_width, scrambling=True, s
                 cdc.source.connect(phy.sink)
             ]
 
-        self.sync.jesd += self.ready.eq(reduce(and_, [link.ready for link in links]))
+        self.sync.jesd += self.ready.eq(Reduce("AND", [link.ready for link in links]))
 
     def register_jsync(self, jsync, polarity=0b0):
         self.jsync_registered = True
@@ -303,9 +302,9 @@ def __init__(self, phys, jesd_settings, converter_data_width, scrambling=True, i
             ]
 
         self.sync.jesd += [
-            self.jsync.eq(reduce(and_, [link.jsync for link in links])),
+            self.jsync.eq(Reduce("AND", [link.jsync for link in links])),
             If(lmfc.zero,
-                self.ready.eq(reduce(and_, [link.ready for link in links]))
+                self.ready.eq(Reduce("AND", [link.ready for link in links]))
             ),
         ]