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setup.py: 2024.08 release. ci #440: Commit b96a625 pushed by enjoy-digital
September 27, 2024 07:47 12m 8s master
master
September 27, 2024 07:47 12m 8s
ci ci #439: by enjoy-digital
September 27, 2024 07:45 12m 2s 2024.08
2024.08
September 27, 2024 07:45 12m 2s
liteeth/phy/rmii: Add 10Mbps/100MBps dynamic speed support. ci #438: Commit 880bdf4 pushed by enjoy-digital
September 26, 2024 10:57 9m 57s master
master
September 26, 2024 10:57 9m 57s
Merge pull request #172 from VOGL-electronic/phy_rmii_fix_efinix_sdr ci #437: Commit 7f91ebb pushed by enjoy-digital
September 26, 2024 09:55 9m 56s master
master
September 26, 2024 09:55 9m 56s
Merge pull request #173 from trabucayre/efinix_rework_clkinput_pll ci #436: Commit 90b1a18 pushed by enjoy-digital
September 26, 2024 09:51 9m 49s master
master
September 26, 2024 09:51 9m 49s
phy/trionrgmii,titaniumrgmii: replaces str by ClockSignal for ClkInput and PLL ci #435: Pull request #173 opened by trabucayre
September 26, 2024 09:04 9m 44s trabucayre:efinix_rework_clkinput_pll
trabucayre:efinix_rework_clkinput_pll
September 26, 2024 09:04 9m 44s
phy/rmii: fix it for efinix ci #434: Pull request #172 opened by maass-hamburg
September 25, 2024 15:08 11m 20s VOGL-electronic:phy_rmii_fix_efinix_sdr
VOGL-electronic:phy_rmii_fix_efinix_sdr
September 25, 2024 15:08 11m 20s
liteeth/mac/core: Allow PHY to enforce with_preamble_crc/with_padding… ci #433: Commit 2b0156e pushed by enjoy-digital
September 23, 2024 14:35 10m 23s master
master
September 23, 2024 14:35 10m 23s
phy/rmii: Cosmetic cleanups. ci #432: Commit 1d19de0 pushed by enjoy-digital
September 23, 2024 13:30 9m 43s master
master
September 23, 2024 13:30 9m 43s
phy/rmii/LiteEthPHYRMIIRX: Avoid reset on converter and improve frame… ci #431: Commit 5438ff0 pushed by enjoy-digital
September 23, 2024 10:23 9m 51s master
master
September 23, 2024 10:23 9m 51s
CONTRIBUTORS: Update. ci #430: Commit a75f4e5 pushed by enjoy-digital
September 20, 2024 10:28 9m 56s master
master
September 20, 2024 10:28 9m 56s
frontend/etherbone/LiteEthEtherbonePacketRX: Only enable LiteEthLastH… ci #429: Commit dd1988a pushed by enjoy-digital
September 20, 2024 10:15 9m 48s master
master
September 20, 2024 10:15 9m 48s
core: Expose icmp_fifo_depth paramter. ci #428: Commit d5a9f9d pushed by enjoy-digital
September 19, 2024 20:19 12m 10s master
master
September 19, 2024 20:19 12m 10s
Merge pull request #171 from GustavsC/master ci #427: Commit b61c3e5 pushed by enjoy-digital
September 18, 2024 09:19 10m 38s master
master
September 18, 2024 09:19 10m 38s
Merge pull request #169 from VOGL-electronic/fix_phy_rmii_efinix ci #425: Commit 5bc0ec0 pushed by enjoy-digital
September 17, 2024 19:20 10m 28s master
master
September 17, 2024 19:20 10m 28s
phy/xgmii: Add Clk/Data Pads definition to avoid duplication in PHYs. ci #424: Commit b573e12 pushed by enjoy-digital
September 16, 2024 09:35 10m 13s master
master
September 16, 2024 09:35 10m 13s
phy: rmii: use ClockSignal(refclk_cd) to drive DDROutput ci #423: Pull request #169 opened by maass-hamburg
September 13, 2024 10:08 10m 22s VOGL-electronic:fix_phy_rmii_efinix
VOGL-electronic:fix_phy_rmii_efinix
September 13, 2024 10:08 10m 22s
frontend/stream: Add 64-bit data_width support. ci #422: Commit 78513c2 pushed by enjoy-digital
September 12, 2024 16:46 10m 7s master
master
September 12, 2024 16:46 10m 7s
frontend/etherbone: Add LiteEthLastHandler to LiteEthEtherbonePacketR… ci #421: Commit b1f916a pushed by enjoy-digital
September 12, 2024 11:34 10m 30s master
master
September 12, 2024 11:34 10m 30s
liteeth_gen: Add XGMII PHY support (Transceiver still need to be inte… ci #420: Commit a2a862d pushed by enjoy-digital
September 11, 2024 13:21 10m 22s master
master
September 11, 2024 13:21 10m 22s
Merge pull request #168 from trabucayre/efinix_rework_primitives ci #419: Commit 74bd085 pushed by trabucayre
September 10, 2024 16:41 9m 54s master
master
September 10, 2024 16:41 9m 54s
Efinix rework primitives ci #418: Pull request #168 opened by trabucayre
September 10, 2024 10:11 10m 2s trabucayre:efinix_rework_primitives
trabucayre:efinix_rework_primitives
September 10, 2024 10:11 10m 2s
ci ci #417: by trabucayre
September 4, 2024 12:48 10m 20s master
master
September 4, 2024 12:48 10m 20s
phy/trionrgmii.py: fixed RX and TX sides. RX: forces phase align by u… ci #416: Commit ecaebfe pushed by trabucayre
September 3, 2024 12:10 10m 23s master
master
September 3, 2024 12:10 10m 23s
Merge pull request #167 from VOGL-electronic/fix_liteethmac ci #415: Commit 9780327 pushed by enjoy-digital
August 27, 2024 07:20 12m 8s master
master
August 27, 2024 07:20 12m 8s