v0.9.6

What's Changed

• Fixed: REL v1, v2 alignment regression (9dfdbb9)
  • Alignment after section data and before relocations / import table is exclusive to REL v3.

Full Changelog: v0.9.5...v0.9.6

v0.9.5

What's Changed

• Fixed: Fix .note.split warnings for older mwld versions (d9817f6)
  • Prior to mwld GC 3.0a3, the linker doesn't support ELF .note sections properly. With GC 2.7, it crashes if the section type is SHT_NOTE. This adjusts the .note.split section type based on mw_comment_version to be compatible with every linker version.
• Added: Add TGC disc support (c403931)
• Added: PureVirtual/Virtual Block2 DWARF attributes by @1superchip in #70

Full Changelog: v0.9.4...v0.9.5

v0.9.4

What's Changed

Add split order attribute for manual reordering (b6a29fa)

Example in splits.txt:

file1.cpp: order:0
  ...

file2.cpp: order:1
  ...

file3.cpp: order:2
  ...

This ensures that file2.cpp is always anchored in between 1 and 3 when resolving the final link order.

Full Changelog: v0.9.3...v0.9.4

v0.9.3

What's Changed

• Added: elf2dol: Support section name denylist by @riidefi in #64
• Added: RSO: make command by @InusualZ in #67
• Added: Support generating RELs with non-sequential module IDs (c484952)
• Fixed: Properly locate ProDG .bss sections by @ieee802dot11ac in #63

Full Changelog: v0.9.2...v0.9.3

v0.9.2

What's Changed

• Added: Update orthrus-ncompress (9c12efa)
  • Significantly faster (and still matching) Yay0/Yaz0 compression.
• Added: Improve REL relocation error handling (e359ea1)
• Fixed: Writing empty v3 RELs (#59)
• Fixed: Match original "exec" for REL sections (761a940)
• Fixed: Create gap symbols at the end of sections (af3bcf5)

Full Changelog: v0.9.1...v0.9.2

v0.9.1

What's Changed

• Added: Detect _savevr/_restvr + check in RELs
• Fixed: Ignore invalid instructions (#55)
• Fixed: Partially revert "Rework section alignment handling (4ea4ec8)
• Fixed: REL alignment after section data (b44aa78)

Full Changelog: v0.9.0...v0.9.1

v0.9.0

What's Changed

• Added: Support address in config symbol references (#58)
  • Example: symbol_name!.data:0x1234, supported in extract and add_relocations in config.yml
• Added: Instruction disassembly in dol diff (#28)
  
• Added: SN GCC DWARF improvements (#46)
• Added: Add U8 (newer .arc) support (46cf0be)
  • Added: u8 list, u8 extract and support for U8 archive paths in config.yml (e.g. orig/SOUE01/files/rels.arc:rels/d_a_asura_bulletNP.rel)
• Fixed: Fix addic/addic. handling in relocation tracker (#57)
• Fixed: Change REL "invalid relocation" to warning (#53)
• Fixed: Check for existing function when analyzing bl (partially #56)

Full Changelog: v0.8.3...v0.9.0

v0.8.3

Support block_relocations and add_relocations in config.yml. This allows more granular control over generated relocations.

Also optimizes relocation address validity checks, leading to ~20% faster relocation analysis.

Config example:

block_relocations:
# Block any relocation pointing to this address.
- target: .data:0x80130140
# Block any relocation originating from this address.
- source: .text:0x80047160
  # (optional) End address to make it a range.
  end: .text:0x800471A8

add_relocations:
# Inserts or overwrites a relocation.
# From: `subi r3, r3, 0x7657`
# To: `li r3, mesWInsert-0x1@sda21`
- source: .text:0x800473F4
  type: sda21
  target: mesWInsert
  addend: -1

Full Changelog: v0.8.2...v0.8.3

v0.8.2

What's Changed

• Fixed: Invalid asm output (bf0d1a8)

Full Changelog: v0.8.1...v0.8.2

v0.8.1

What's Changed

• Fixed: .note.split generation by @cadmic in encounter/objdiff#61

Full Changelog: v0.8.0...v0.8.1