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riscv64: Implement a few SIMD arithmetic ops (bytecodealliance#6268)
* riscv64: Swap order of `VecAluRRR` source registers These were accidentally reversed from what we declare in the isle emit helper * riscv64: Add SIMD `isub` * riscv64: Add SIMD `imul` * riscv64: Add `{u,s}mulhi` * riscv64: Add `b{and,or,xor}` * cranelift: Move `imul.i8x16` runtest to separate file Looks like x86 does not implement it * riscv64: Better formatting for `VecAluOpRRR` * cranelift: Enable x86 SIMD tests with `has_sse41=false`
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,73 @@ | ||
test compile precise-output | ||
set unwind_info=false | ||
target riscv64 has_v | ||
|
||
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||
function %band_i8x16(i8x16, i8x16) -> i8x16 { | ||
block0(v0: i8x16, v1: i8x16): | ||
v2 = band v0, v1 | ||
return v2 | ||
} | ||
|
||
; VCode: | ||
; block0: | ||
; vand.vv v10,v10,v11 #avl=16, #vtype=(e8, m1, ta, ma) | ||
; ret | ||
; | ||
; Disassembled: | ||
; block0: ; offset 0x0 | ||
; .byte 0x57, 0x70, 0x08, 0xcc | ||
; .byte 0x57, 0x85, 0xa5, 0x26 | ||
; ret | ||
|
||
function %band_i16x8(i16x8, i16x8) -> i16x8 { | ||
block0(v0: i16x8, v1: i16x8): | ||
v2 = band v0, v1 | ||
return v2 | ||
} | ||
|
||
; VCode: | ||
; block0: | ||
; vand.vv v10,v10,v11 #avl=8, #vtype=(e16, m1, ta, ma) | ||
; ret | ||
; | ||
; Disassembled: | ||
; block0: ; offset 0x0 | ||
; .byte 0x57, 0x70, 0x84, 0xcc | ||
; .byte 0x57, 0x85, 0xa5, 0x26 | ||
; ret | ||
|
||
function %band_i32x4(i32x4, i32x4) -> i32x4 { | ||
block0(v0: i32x4, v1: i32x4): | ||
v2 = band v0, v1 | ||
return v2 | ||
} | ||
|
||
; VCode: | ||
; block0: | ||
; vand.vv v10,v10,v11 #avl=4, #vtype=(e32, m1, ta, ma) | ||
; ret | ||
; | ||
; Disassembled: | ||
; block0: ; offset 0x0 | ||
; .byte 0x57, 0x70, 0x02, 0xcd | ||
; .byte 0x57, 0x85, 0xa5, 0x26 | ||
; ret | ||
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||
function %band_i64x2(i64x2, i64x2) -> i64x2 { | ||
block0(v0: i64x2, v1: i64x2): | ||
v2 = band v0, v1 | ||
return v2 | ||
} | ||
|
||
; VCode: | ||
; block0: | ||
; vand.vv v10,v10,v11 #avl=2, #vtype=(e64, m1, ta, ma) | ||
; ret | ||
; | ||
; Disassembled: | ||
; block0: ; offset 0x0 | ||
; .byte 0x57, 0x70, 0x81, 0xcd | ||
; .byte 0x57, 0x85, 0xa5, 0x26 | ||
; ret | ||
|
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,73 @@ | ||
test compile precise-output | ||
set unwind_info=false | ||
target riscv64 has_v | ||
|
||
|
||
function %bor_i8x16(i8x16, i8x16) -> i8x16 { | ||
block0(v0: i8x16, v1: i8x16): | ||
v2 = bor v0, v1 | ||
return v2 | ||
} | ||
|
||
; VCode: | ||
; block0: | ||
; vor.vv v10,v10,v11 #avl=16, #vtype=(e8, m1, ta, ma) | ||
; ret | ||
; | ||
; Disassembled: | ||
; block0: ; offset 0x0 | ||
; .byte 0x57, 0x70, 0x08, 0xcc | ||
; .byte 0x57, 0x85, 0xa5, 0x2a | ||
; ret | ||
|
||
function %bor_i16x8(i16x8, i16x8) -> i16x8 { | ||
block0(v0: i16x8, v1: i16x8): | ||
v2 = bor v0, v1 | ||
return v2 | ||
} | ||
|
||
; VCode: | ||
; block0: | ||
; vor.vv v10,v10,v11 #avl=8, #vtype=(e16, m1, ta, ma) | ||
; ret | ||
; | ||
; Disassembled: | ||
; block0: ; offset 0x0 | ||
; .byte 0x57, 0x70, 0x84, 0xcc | ||
; .byte 0x57, 0x85, 0xa5, 0x2a | ||
; ret | ||
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||
function %bor_i32x4(i32x4, i32x4) -> i32x4 { | ||
block0(v0: i32x4, v1: i32x4): | ||
v2 = bor v0, v1 | ||
return v2 | ||
} | ||
|
||
; VCode: | ||
; block0: | ||
; vor.vv v10,v10,v11 #avl=4, #vtype=(e32, m1, ta, ma) | ||
; ret | ||
; | ||
; Disassembled: | ||
; block0: ; offset 0x0 | ||
; .byte 0x57, 0x70, 0x02, 0xcd | ||
; .byte 0x57, 0x85, 0xa5, 0x2a | ||
; ret | ||
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||
function %bor_i64x2(i64x2, i64x2) -> i64x2 { | ||
block0(v0: i64x2, v1: i64x2): | ||
v2 = bor v0, v1 | ||
return v2 | ||
} | ||
|
||
; VCode: | ||
; block0: | ||
; vor.vv v10,v10,v11 #avl=2, #vtype=(e64, m1, ta, ma) | ||
; ret | ||
; | ||
; Disassembled: | ||
; block0: ; offset 0x0 | ||
; .byte 0x57, 0x70, 0x81, 0xcd | ||
; .byte 0x57, 0x85, 0xa5, 0x2a | ||
; ret | ||
|
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