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Ensure vextractf64x4 and vextracti64x4 aren't marked DstDstSrc #85030

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Apr 19, 2023
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Ensure vextractf64x4 and vextracti64x4 aren't marked DstDstSrc #85030

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4 changes: 2 additions & 2 deletions src/coreclr/jit/instrsxarch.h
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Expand Up @@ -611,8 +611,8 @@ INST3(FIRST_AVX512_INSTRUCTION, "FIRST_AVX512_INSTRUCTION", IUM_WR, BAD_CODE, BA
INST3(kmovw_gpr, "kmovw", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x92), INS_TT_NONE, REX_W0 | Encoding_VEX | KInstruction)
INST3(kmovw_msk, "kmovw", IUM_WR, PCKFLT(0x91), BAD_CODE, PCKFLT(0x90), INS_TT_NONE, REX_W0 | Encoding_VEX | KInstruction)
INST3(kortestw, "kortestw", IUM_WR, BAD_CODE, BAD_CODE, PCKFLT(0x98), INS_TT_NONE, REX_W0 | Encoding_VEX | Resets_OF | Resets_SF | Writes_ZF | Resets_AF | Resets_PF | Writes_CF | KInstruction)
INST3(vextractf64x4, "extractf64x4", IUM_WR, SSE3A(0x1B), BAD_CODE, BAD_CODE, INS_TT_TUPLE4, Input_64Bit | REX_W1_EVEX | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // Extract 256-bit packed double-precision floating point values
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@tannergooding tannergooding Apr 19, 2023 •
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DstDstSrc, DstSrcSrc, and others are somewhat "poor" names.

They originally existed because we didn't have proper VEX support and everything was considered RMW. So, when we went from encoding things in ModRM:reg and ModRM:r/m into also having a new VEX.vvvv "field", we needed a way to track how that field should be encoded without also doing the more significant work around "properly" supporting VEX and treating things as non-RMW

Since the vast majority of instructions were of the form ins reg, r/m these flags were basically used to indicate whether we duplicated the Dst (ModRM:reg) or Src (ModRM:r/m) register into the VEX.vvvv field. -- This "worked" because we also didn't really support containment for stores of hwintrinsics at all, so we never really had to care about ModRM:r/m being the Dst.

Today, we do support VEX properly, don't require everything to be viewed as RMW, and do also support generating stores for HWIntrinsics. So, it might be good to rethink the flag names a bit in the near future. Namely, we really just care about which operands go into which of the three ModRM:reg, VEX.vvvv, and ModRM:r/m (with that particular order for Dst, Op1, Op2 being the most common) and so there's probably something there in how we track things that will end up working and being clearer as to what it means

INST3(vextracti64x4, "extracti64x4", IUM_WR, SSE3A(0x3B), BAD_CODE, BAD_CODE, INS_TT_TUPLE4, Input_64Bit | REX_W1_EVEX | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // Extract 256-bit packed quadword integer values
INST3(vextractf64x4, "extractf64x4", IUM_WR, SSE3A(0x1B), BAD_CODE, BAD_CODE, INS_TT_TUPLE4, Input_64Bit | REX_W1_EVEX | Encoding_EVEX) // Extract 256-bit packed double-precision floating point values
INST3(vextracti64x4, "extracti64x4", IUM_WR, SSE3A(0x3B), BAD_CODE, BAD_CODE, INS_TT_TUPLE4, Input_64Bit | REX_W1_EVEX | Encoding_EVEX) // Extract 256-bit packed quadword integer values
INST3(vinsertf64x4, "insertf64x4", IUM_WR, BAD_CODE, BAD_CODE, SSE3A(0x1A), INS_TT_TUPLE4, Input_64Bit | REX_W1_EVEX | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // Insert 256-bit packed double-precision floating point values
INST3(vinserti64x4, "inserti64x4", IUM_WR, BAD_CODE, BAD_CODE, SSE3A(0x3A), INS_TT_TUPLE4, Input_64Bit | REX_W1_EVEX | Encoding_EVEX | INS_Flags_IsDstDstSrcAVXInstruction) // Insert 256-bit packed quadword integer values
INST3(vmovdqa64, "movdqa64", IUM_WR, PCKDBL(0x7F), BAD_CODE, PCKDBL(0x6F), INS_TT_FULL_MEM, Input_64Bit | REX_W1_EVEX | Encoding_EVEX)
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