gateware-20230506
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17 commits
to master
since this release
Pipelining This is a major rewrite, pipelining all modules in the SID chip in order to save FPGA resources: * Power-on initialization of oscillators, noise LFSRs, and envelope counters * Register writes * Update and synchronization of oscillators * Waveform generation * Envelope generation * Voice DCA * Filter / audio output