Version 4.6.85.10 (cherry-pick)

Merged 434a291 Make FlushICache NOP for Nvidia Denver 1.0 only R=bmeurer@chromium.org, rodolph.perfetta@arm.com BUG=v8:4398 NOTRY=true NOPRESUBMIT=true Review URL: https://codereview.chromium.org/1323813002 Cr-Commit-Position: refs/branch-heads/4.6@{#13} Cr-Branched-From: 24d34a8-refs/heads/4.6.85@{#1} Cr-Branched-From: 8f44118-refs/heads/master@{#30256}
crosswalk-project · Sep 1, 2015 · 5d95a88 · 5d95a88
1 parent 6a97bcb
commit 5d95a88
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Showing 3 changed files with 7 additions and 2 deletions.
diff --git a/src/arm/assembler-arm.cc b/src/arm/assembler-arm.cc
@@ -126,7 +126,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   if (FLAG_enable_32dregs && cpu.has_vfp3_d32()) supported_ |= 1u << VFP32DREGS;
 
   if (cpu.implementer() == base::CPU::NVIDIA &&
-      cpu.variant() == base::CPU::NVIDIA_DENVER) {
+      cpu.variant() == base::CPU::NVIDIA_DENVER &&
+      cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
     supported_ |= 1u << COHERENT_CACHE;
   }
 #endif

diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
@@ -52,7 +52,8 @@ void CpuFeatures::ProbeImpl(bool cross_compile) {
   // Probe for runtime features
   base::CPU cpu;
   if (cpu.implementer() == base::CPU::NVIDIA &&
-      cpu.variant() == base::CPU::NVIDIA_DENVER) {
+      cpu.variant() == base::CPU::NVIDIA_DENVER &&
+      cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
     supported_ |= 1u << COHERENT_CACHE;
   }
 }

diff --git a/src/base/cpu.h b/src/base/cpu.h
@@ -59,6 +59,9 @@ class CPU final {
   static const int ARM_CORTEX_A12 = 0xc0c;
   static const int ARM_CORTEX_A15 = 0xc0f;
 
+  // Denver-specific part code
+  static const int NVIDIA_DENVER_V10 = 0x002;
+
   // PPC-specific part codes
   enum {
     PPC_POWER5,