UVM / SystemVerilog Developer
FPGA Design Engineer.
PYTHON 3 Developer.
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Michael Hughes
- USA
Popular repositories Loading
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UVM_Command_Center
UVM_Command_Center PublicUVM Command Center - UVM Testbench Builder (DEMO) - Demo of UVM Verification Workflow IDE.
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UVMTEMPLATES
UVMTEMPLATES PublicUVM Templates for Rapid Implementation of Universal Verification Methodology FPGA/ASIC/SOC Testbenches.
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contactcloud
contactcloud PublicWindows Contact Management Software Application written in PYTHON and built with cx_Freeze.
Python
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