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Allow Side Effecting Statement to have Names #2057

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merged 24 commits into from
Feb 17, 2021

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ekiwi
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@ekiwi ekiwi commented Jan 26, 2021

TODO:

  • test that a circuit which has a name collision with a named statement is rejected
  • test that a circuit which contains a reference to a statement is rejected
  • add new feature to the firrtl spec

Contributor Checklist

  • Did you add Scaladoc to every public function/method?
  • Did you update the FIRRTL spec to include every new feature/behavior?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
  • Did you specify the type of improvement?
  • Did you state the API impact?
  • Did you specify the code generation impact?
  • Did you request a desired merge strategy?
  • Did you add text to be included in the Release Notes for this change?

Type of Improvement

  • new feature: named print, stop and verification statements

API Impact

  • extends Print, Stop and Verification nodes with a name field
  • statement labels are intentionally kept optional so that old firrtl should parse and work with no problem

Backend Code Generation Impact

  • this should not change the Verilog at the moment

Desired Merge Strategy

  • squash

Release Notes

  • print, stop, assume, assert and cover statements can now be given a name which allows them to be annotated

Reviewer Checklist (only modified by reviewer)

  • Did you add the appropriate labels?
  • Did you mark the proper milestone (1.2.x, 1.3.0, 1.4.0) ?
  • Did you review?
  • Did you check whether all relevant Contributor checkboxes have been checked?
  • Did you mark as Please Merge?

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@davidbiancolin davidbiancolin left a comment

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Pretty cool, i've been wanting this feature for a while. I think adding the trait might clean up the pattern matching a little bit and make it easier to add other similar nodes in the future, but i'll defer to you.

What's the chisel strategy going to be for emitting these names?

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src/main/scala/firrtl/ir/IR.scala Outdated Show resolved Hide resolved
src/main/scala/firrtl/passes/CheckHighForm.scala Outdated Show resolved Hide resolved
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@jackkoenig jackkoenig left a comment

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Looks really good overall, some minor comments.

src/main/scala/firrtl/ir/Serializer.scala Outdated Show resolved Hide resolved
src/main/scala/firrtl/passes/Inline.scala Outdated Show resolved Hide resolved
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@ekiwi ekiwi force-pushed the stmt-lbl branch 2 times, most recently from ba0441c to 9ceefba Compare February 15, 2021 20:08
pred: Expression,
en: Expression,
msg: StringLit,
@since("FIRRTL 1.5") name: String = "")
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This is super minor, but I think it'd be nice to have a newline between the @since and name just so that the types are spaced over so much

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LGTM

@ekiwi ekiwi added the Please Merge Accepted PRs that are ready to be merged. Useful when waiting on CI. label Feb 17, 2021
@mergify mergify bot merged commit 5a89fca into chipsalliance:master Feb 17, 2021
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4 participants