Chisel v6.4.0

Features

• [LTL] Added overloadings for AssertProperty (backport #4037) (by @mergify[bot] in #4041)
• Add modulePorts and fullModulePorts in DataMirror for Instance (backport #4076) (by @mergify[bot] in #4077)
  Added modulePorts and fullModulePorts methods in DataMirror that returns all ports on an Instance of a module.

API Modification

• checkTypeEquivalence now considers ProbeInfo (backport #4064) (by @mergify[bot] in #4112)
  Now checkTypeEquivalence will check whether data have the same probe type modifier including writeability and color (layer).

API Deprecation

• Deprecate AssertPropertyLike.createIntrinsic (by @jackkoenig in #4059)
  It should never have been a public API.
• Make it a warning to have too-wide literal values in Bundle Literals (backport #4093) (by @mergify[bot] in #4095)

Fixes

• Fix Nested Instantiate (backport #4018) (by @mergify[bot] in #4027)
  Fix Nested Instantiate
• Fix Typo in ExtractFromVecSizeZero warning message (backport #4029) (by @mergify[bot] in #4031)
• Add support for Vec literals of empty Vecs (backport #4070) (by @mergify[bot] in #4073)
• Fix literal handling for views of empty Aggregates (backport #4071) (by @mergify[bot] in #4075)
  Previously, a view of an empty aggregate would incorrectly always have a litValue of 0.
• Materialize wires for .ref of Aggregate views (backport #4080) (by @mergify[bot] in #4086)
  Fix muxing and probing of views of Aggregates
• [SVSim] Fixed non-firing AssertProperty in SVSim (backport #4087) (by @mergify[bot] in #4089)
  • [SVSim] Fixed AssertProperty failing to fire in verilator simulation.
• Fix widths for literal values in Bundle literals (backport #4082) (by @mergify[bot] in #4092)
  Previously, the user-specified (or unspecified minimum width) of the literal would be used in some operations like concatenation. For literal values that are too-wide, they will now truncate to the correct width. This will become a warning (then later an error) in newer major versions of Chisel.
• BoringUtils: Fix tapAndRead to return same type even when not boring. (backport #4084) (by @mergify[bot] in #4094)
  Always return fully aligned result from tapAndRead, even if no boring performed.
• Don't warn when 0.U used as value for 0-bit BundleLit field (backport #4097) (by @mergify[bot] in #4098)
• Fix boring tap of non-passive source from parent. (backport #4083) (by @mergify[bot] in #4096)
  Fix tapping mix-alignment signal from parent.
• Fix 0 width signals chiselsim (backport #4100) (by @mergify[bot] in #4104)
  Fix failing ChiselSim/SVsim error to simulate modules with zero-width ports.
• Support views of ports in ChiselSim (backport #4107) (by @mergify[bot] in #4110)
  Also fix reifySingleData to return the Data itself if it is not a view.
• FixedIO__Modules with various kinds of probe ports (backport #4105) (by @mergify[bot] in #4111)
  Fix for #4102. Now supported are FlatIO (and therefore FixedIO___Module) of:
  • Probe(Element)
  • Probe(Aggregate)
  • Aggregate(Probes)
  • Aggregates containing any of the above
• Fix svsim with gcc14 (backport #4121) (by @mergify[bot] in #4123)

Dependency Updates

• Add Scala 2.13.14 to cross-build (backport #4044) (by @mergify[bot] in #4047)

Build and Internal Changes

• [6.x] Enable MiMa for v6.3.0 (by @chiselbot in #4017)
• [ci] Stop copying body over to backports in backport-fixup (backport #4005) (by @mergify[bot] in #4043)
• add test for FlatIO port ordering (backport #4113) (by @mergify[bot] in #4115)
  Added a unit test for FlatIO Ordering being maintained
• Bump versions of Github actions to versions using Node 20 (backport #4116) (by @mergify[bot] in #4118)
• Add and use Mill wrapper script (backport #4119) (by @mergify[bot] in #4125)

Full Changelog: v6.3.0...v6.4.0