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systemz: pad instruction width up to 6 bytes #1679

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merged 1 commit into from
Sep 3, 2020

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carenas
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@carenas carenas commented Sep 3, 2020

instructions could be 2, 4 or 6 bytes so pad accordingly as it
was done on the other CISC architecture.

instructions could be 2, 4 or 6 bytes so pad accordingly as it
was done on the other CISC architecture.
@aquynh aquynh merged commit 47f05e0 into capstone-engine:master Sep 3, 2020
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aquynh commented Sep 3, 2020

merged, thanks!

@carenas carenas deleted the s390x branch September 3, 2020 08:52
aquynh pushed a commit that referenced this pull request Sep 16, 2020
instructions could be 2, 4 or 6 bytes so pad accordingly as it
was done on the other CISC architecture.
aquynh pushed a commit that referenced this pull request Sep 16, 2020
instructions could be 2, 4 or 6 bytes so pad accordingly as it
was done on the other CISC architecture.
@riptl riptl mentioned this pull request Jul 22, 2022
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2 participants