Fix cmp register access on aarch64 #1655
Merged
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This pr fixes #1653
I noticed that the problem relies on the fact that
cmp x0, x1
is in fact alias forsubs xzr, x0, x1
.Now, when the method
printAliasInstruction
callsprintOperand
, it passes the correct operand number (skips the first register xzr, and asks for x0); howeverprintOperand
then usesMI->ac_idx
to address which reg access information to return back - and this is wrong, as MI->ac_idx is initialized with 0 and it should use the properOpNum
argument that is passed toprintOperand
IMHO
MI->ac_idx
is an artifact from arm32 that got carried over to the arm64 implementation, and as we don't need to deal with multiple register edge cases likepop {r1,r2,r3,r4...}
I don't see the need forMI->ac_idx
at all for arch64, but I am probably wrong (this is my first contribution to the project), let me know what do you think @aquynh .This pr will fix also register access for other instructions that are actually aliases and hide a register like
tst x0, x1
.