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RISCV support ISRV32/ISRV64 #1401
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… the TableGen files generated from llvm-tblgen. Add Disassembler.h
…ler_getInstruction, and RISCV_getInstruction
…o RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
…nor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
…Info.inc, RISCVModule.c. Working on riscv.h
…DDI, AND works properly.
…and test_iter to work w/ the current code strcuture
…ents in struct initializer). Added RISCV tests to test_iter.c
Need add OPT? I will fix this when the RISCVC PR. |
i mean simply add this to riscv.h:
if you dont want to, never mind. |
looks like already fixed, will depend on current instruction print |
there is one issue: you are using internal autogen register names, so the public register ID must follow the enum in RISCVGenRegisterInfo.inc. you can see that cs_reg_name calls RISCV_reg_name(), which calls getRegisterName(). for this to work, the RISC_REG_xxx must match the enum in RISCVGenRegisterInfo.inc. however, these dont match, for example:
meanwhile:
you did not have this problem before, when you used now you can either make them match, or recover that |
the mismatch starts from floating point registers, but not before that. this is why we dont have see any issues with another thing: given the current approach, we need to have alias registers in
users may ask where these RA, SP, GP registers are from, as they are nowhere in (after update |
one more issue is that |
fix consistency with RISCVGenRegisterInfo.inc. |
cool, lets finish this with alias registers added to riscv.h (then update binding constants after that) |
That is just S0, but how about all other alias registers? |
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For ex, look at the output of test_riscv.c, what is s1 register? There is
no such a thing in riscv.h.
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I write after the comments. |
No, we need the alias that users can use, not just comments.
And please uppercase, like "FP", "S0", but not "fp", "s0".
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RISCV_REG_X8_s0
Please just use RISCV_REG_S0
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what's the difference??? |
Just to align with the current naming scheme.
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i will merge. please stay around to help to maintain this work. |
merged, thanks everyone for the amazing effort! |
cheers, hope have the opportunity to see you offline. |
Hope to see you in BJ, i guess? |
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Fixes: a012f75 ("RISCV support ISRV32/ISRV64 (capstone-engine#1401)")
This is based on PR#1198 and LLVM upstream commit b81d715c(Sat Feb 16 18:39:14 2019).
Also referenced the SyestemZ TableGen patchs.
I also add the TableGen patch at capstone/contrib/update_riscv.