Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

riscv64: Optimize storing zero to memory by using zero_reg #8719

Merged
merged 3 commits into from
May 31, 2024
Merged

riscv64: Optimize storing zero to memory by using zero_reg #8719

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
1606c88
riscv64: Optimize storing zero to memory by using `zero_reg`
alexcrichton May 28, 2024
371c30e
Fix lowerings of `istore{8,16,32}`
alexcrichton May 31, 2024
17ad1f7
Add test for compressed stores
alexcrichton May 31, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
19 changes: 17 additions & 2 deletions cranelift/codegen/src/isa/riscv64/inst.isle
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2438,8 +2438,23 @@
dst))

;; helper function to store to memory.
(decl gen_store (AMode StoreOP MemFlags Reg) InstOutput)
(rule (gen_store amode op flags src)
;;
;; This helper contains a special-case for zero constants stored to memory to
;; directly store the `zero` register to memory. See #7162 for some discussion
;; on why this doesn't just fall out.
(decl gen_store (AMode MemFlags Value) InstOutput)
(rule 1 (gen_store amode flags val @ (value_type ty))
(if-let (u64_from_iconst 0) val)
(rv_store amode (store_op ty) flags (zero_reg)))
(rule 0 (gen_store amode flags val @ (value_type ty))
(rv_store amode (store_op ty) flags val))

;; Emit a raw instruction to store a register into memory.
;;
;; Note that the `src` operand must have the correct type for the `op`
;; specified.
(decl rv_store (AMode StoreOP MemFlags Reg) InstOutput)
(rule (rv_store amode op flags src)
(side_effect (SideEffectNoResult.Inst (MInst.Store amode op flags src))))


Expand Down
12 changes: 6 additions & 6 deletions cranelift/codegen/src/isa/riscv64/lower.isle
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2098,24 +2098,24 @@

;;;;; Rules for `istore8`;;;;;;;;;
(rule (lower (istore8 flags src addr offset))
(gen_store (amode addr offset) (StoreOP.Sb) flags src))
(rv_store (amode addr offset) (StoreOP.Sb) flags src))

;;;;; Rules for `istore16`;;;;;;;;;
(rule (lower (istore16 flags src addr offset))
(gen_store (amode addr offset) (StoreOP.Sh) flags src))
(rv_store (amode addr offset) (StoreOP.Sh) flags src))

;;;;; Rules for `istore32`;;;;;;;;;
(rule (lower (istore32 flags src addr offset))
(gen_store (amode addr offset) (StoreOP.Sw) flags src))
(rv_store (amode addr offset) (StoreOP.Sw) flags src))

;;;;; Rules for `store`;;;;;;;;;
(rule (lower (store flags src @ (value_type ty) addr offset))
(gen_store (amode addr offset) (store_op ty) flags src))
(gen_store (amode addr offset) flags src))

(rule 1 (lower (store flags src @ (value_type $I128) addr offset))
(if-let offset_plus_8 (s32_add_fallible offset 8))
(let ((_ InstOutput (gen_store (amode addr offset) (StoreOP.Sd) flags (value_regs_get src 0))))
(gen_store (amode addr offset_plus_8) (StoreOP.Sd) flags (value_regs_get src 1))))
(let ((_ InstOutput (rv_store (amode addr offset) (StoreOP.Sd) flags (value_regs_get src 0))))
(rv_store (amode addr offset_plus_8) (StoreOP.Sd) flags (value_regs_get src 1))))

(rule 2 (lower (store flags src @ (value_type (ty_vec_fits_in_register ty)) addr offset))
(let ((eew VecElementWidth (element_width_from_type ty))
Expand Down
Loading