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riscv64: Improve base select lowering #8703
riscv64: Improve base select lowering #8703
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; mv a4, a0 | ||
; mv a0, a4 |
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We now sometimes get this funky output from regalloc. I think I understand why it's doing this, but maybe there's some way to avoid this?
As a side note, maybe we could force the destination register to always be the same as one of the inputs. We would always emit the 2 instruction select and let regalloc emit the move beforehand if it finds it beneficial.
I'm not sure if this is better or not.
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I'm positive toward this change but someone more familiar with RISC-V should probably review this? |
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Last commit LGTM, thanks! Happy to land once #8695 does and this rebases.
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👋 Hey,
This PR is an attempt at improving the base lowering for the
select
instruction in the RISC-V backend. It reduces one instruction from the current lowering.Currently our selects have the following instructions:
With this change we now produce the following:
So, we lose the jump instruction, but one of the moves becomes unconditional. This to me feels like it's worth it, but I have no data to prove one way or the other, and I think if i try to measure it with sightglass it probably won't detect this change.
One of the benefits of this lowering is that now if one of the input registers is the same as the destination register we can do a two instruction select, like so (assuming
rx = rd
):I've had to do some regalloc surgery to make that possible which makes some other cases get worse regalloc.
This is built on top of #8695, but only the last commit is relevant.