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riscv64: Fix missing extensions for 8/16-bit div/rem #7268

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merged 1 commit into from
Oct 17, 2023
Merged

riscv64: Fix missing extensions for 8/16-bit div/rem #7268

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6 changes: 3 additions & 3 deletions cranelift/codegen/src/isa/riscv64/lower.isle
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Original file line number Diff line number Diff line change
Expand Up @@ -556,7 +556,7 @@
(rule 1 (lower (has_type (fits_in_16 ty) (sdiv x y @ (iconst imm))))
(if-let $true (has_m))
(if (safe_divisor_from_imm64 ty imm))
(rv_divw (sext x) y))
(rv_divw (sext x) (sext y)))

(rule 2 (lower (has_type $I32 (sdiv x y)))
(if-let $true (has_m))
Expand Down Expand Up @@ -604,7 +604,7 @@
(rule 1 (lower (has_type (fits_in_16 ty) (urem x y @ (iconst imm))))
(if-let $true (has_m))
(if (safe_divisor_from_imm64 ty imm))
(rv_remuw (zext x) y))
(rv_remuw (zext x) (zext y)))

(rule 2 (lower (has_type $I32 (urem x y)))
(if-let $true (has_m))
Expand Down Expand Up @@ -633,7 +633,7 @@
(rule 1 (lower (has_type (fits_in_16 ty) (srem x y @ (iconst imm))))
(if-let $true (has_m))
(if (safe_divisor_from_imm64 ty imm))
(rv_remw (sext x) y))
(rv_remw (sext x) (sext y)))

(rule 2 (lower (has_type $I32 (srem x y)))
(if-let $true (has_m))
Expand Down
10 changes: 10 additions & 0 deletions cranelift/filetests/filetests/runtests/urem.clif
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Original file line number Diff line number Diff line change
Expand Up @@ -135,3 +135,13 @@ block0(v0: i8):
; run: %urem_imm_i8(-19) == 0
; run: %urem_imm_i8(0xC0) == 0
; run: %urem_imm_i8(0x80) == 2


function %constant_inputs() -> i8 {
block0:
v3 = iconst.i8 208
v11 = urem v3, v3 ; v3 = 208, v3 = 208
return v11
}

; run: %constant_inputs() == 0