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riscv64: Fix encoding for c.addi4spn #7208

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merged 2 commits into from
Oct 11, 2023
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riscv64: Fix encoding for c.addi4spn #7208

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5ce967b
riscv64: Fix encoding for `c.addi4spn`
afonso360 Oct 10, 2023
fdc90b1
riscv64: Add a few more `c.addi4spn` tests
afonso360 Oct 11, 2023
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2 changes: 1 addition & 1 deletion cranelift/codegen/src/isa/riscv64/inst/encode.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -468,7 +468,7 @@ pub fn encode_ciw_type(op: CiwOp, rd: WritableReg, imm: u8) -> u16 {
let mut imm_field = 0;
imm_field |= ((imm >> 1) & 1) << 0;
imm_field |= ((imm >> 0) & 1) << 1;
imm_field |= ((imm >> 4) & 7) << 2;
imm_field |= ((imm >> 4) & 15) << 2;
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imm_field |= ((imm >> 2) & 3) << 6;

let mut bits = 0;
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37 changes: 37 additions & 0 deletions cranelift/filetests/filetests/isa/riscv64/zca.clif
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Expand Up @@ -469,6 +469,43 @@ block0:
; c.addi16sp sp, 0x10
; c.jr ra

function %c_addi4spn_512() -> i64 {
ss0 = explicit_slot 1024

block0:
v0 = stack_addr.i64 ss0+512
return v0
}

; VCode:
; add sp,-16
; sd ra,8(sp)
; sd fp,0(sp)
; mv fp,sp
; add sp,-1024
; block0:
; load_addr a0,512(nominal_sp)
; add sp,+1024
; ld ra,8(sp)
; ld fp,0(sp)
; add sp,+16
; ret
;
; Disassembled:
; block0: ; offset 0x0
; c.addi16sp sp, -0x10
; c.sdsp ra, 8(sp)
; c.sdsp s0, 0(sp)
; c.mv s0, sp
; addi sp, sp, -0x400
; block1: ; offset 0xc
; c.addi4spn a0, sp, 0x200
; addi sp, sp, 0x400
; c.ldsp ra, 8(sp)
; c.ldsp s0, 0(sp)
; c.addi16sp sp, 0x10
; c.jr ra

function %c_li() -> i64 {
block0:
v0 = iconst.i64 1
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