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riscv64: Consolidate conditional moves into one instruction #7145

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Commits on Oct 4, 2023

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  4. riscv64: Consolidate conditional moves into one instruction

    This commit removes the `IntSelect` and `SelectReg` pseudo-instructions
    from the riscv64 backend and consolidates them into the `Select`
    instruction. Additionally the `Select` instruction is updated to subsume
    the functionality of these two previous instructions. Namely `Select`
    now operates with `ValueRegs` to handle i128 and additionally takes an
    `IntegerCompare` as the condition for the conditional branch to use.
    
    This commit touches a fair bit of the backend since conditional
    selection of registers was used in quite a few places. The previous
    `gen_select_*` functions are replaced with new typed equivalents of
    `gen_select_{xreg,vreg,freg,regs}`. Furthermore new `cmp_*` helpers were
    added to create `IntegerCompare` instructions which sort-of match
    conditional branch instructions, or at least the pnemonics they use.
    
    Finally since this affected the `select` CLIF instruction itself I went
    ahead and did some refactoring there too. The `select` instruction
    creates an `IntegerCompare` from its argument to use to generate the
    appropriate register selection instruction. This is basically the same
    thing that `brif` does and now both go through a new helper,
    `lower_int_compare`, which takes a `Value` and produces an
    `IntegerCompare` representing if that value is either true or false.
    This enables folding an `icmp` or an `fcmp`, for example, directly into
    a branching instruction.
    alexcrichton committed Oct 4, 2023
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  5. Fix a test

    alexcrichton committed Oct 4, 2023
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