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riscv64: Implement insertlane #6408

Merged
merged 9 commits into from
May 20, 2023
Merged

riscv64: Implement insertlane #6408

merged 9 commits into from
May 20, 2023

Commits on May 20, 2023

  1. riscv64: Support vector instruction masking

    @afonso360
    afonso360 committed May 20, 2023
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  2. riscv64: Add vmerge instructions

    @afonso360
    afonso360 committed May 20, 2023
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  3. riscv64: Implement insertlane

    @afonso360
    afonso360 committed May 20, 2023
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  4. riscv64: Fix encoding of vmv instructions 

    Some of these carry their source in vs2
    @afonso360
    afonso360 committed May 20, 2023
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  5. riscv64: Fix formatting of mask register 

    Remove the space between , and the register. This
is inline with the rest of our formatting.
    @afonso360
    afonso360 committed May 20, 2023
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  6. riscv64: Restrict insertlane to vector types that fit in a single r… 

    …egister
    @afonso360
    afonso360 committed May 20, 2023
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  7. wasmtime: Enable more RISC-V SIMD tests

    @afonso360
    afonso360 committed May 20, 2023
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  8. riscv64: Use inline format syntax for printing vector instructions

    @afonso360
    afonso360 committed May 20, 2023
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  9. riscv64: Add vector mask note

    @afonso360
    afonso360 committed May 20, 2023
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