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riscv64: Implement a few SIMD arithmetic ops #6268

Merged
merged 8 commits into from
Apr 25, 2023
Merged

riscv64: Implement a few SIMD arithmetic ops #6268

merged 8 commits into from
Apr 25, 2023

Commits on Apr 25, 2023

  1. riscv64: Swap order of VecAluRRR source registers 

    These were accidentally reversed from what we declare in the isle emit helper
    @afonso360
    afonso360 committed Apr 25, 2023
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  2. riscv64: Add SIMD isub

    @afonso360
    afonso360 committed Apr 25, 2023
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  3. riscv64: Add SIMD imul

    @afonso360
    afonso360 committed Apr 25, 2023
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  4. riscv64: Add {u,s}mulhi

    @afonso360
    afonso360 committed Apr 25, 2023
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  5. riscv64: Add b{and,or,xor}

    @afonso360
    afonso360 committed Apr 25, 2023
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  6. cranelift: Move imul.i8x16 runtest to separate file 

    Looks like x86 does not implement it
    @afonso360
    afonso360 committed Apr 25, 2023
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  7. riscv64: Better formatting for VecAluOpRRR

    @afonso360
    afonso360 committed Apr 25, 2023
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  8. cranelift: Enable x86 SIMD tests with has_sse41=false

    @afonso360
    afonso360 committed Apr 25, 2023
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