Remove "breduce"

cranelift/codegen/meta/src/shared/instructions.rs

@@ -3296,27 +3296,6 @@ pub(crate) fn define(
         TypeSetBuilder::new().ints(Interval::All).build(),
     );
 
-    let BoolTo = &TypeVar::new(
-        "BoolTo",
-        "A smaller boolean type",
-        TypeSetBuilder::new().ints(Interval::All).build(),
-    );
-
-    let x = &Operand::new("x", Bool);
-    let a = &Operand::new("a", BoolTo);
-
-    ig.push(
-        Inst::new(
-            "breduce",
-            r#"
-        Convert `x` to a smaller boolean type by discarding the most significant bits.
-        "#,
-            &formats.unary,
-        )
-        .operands_in(vec![x])
-        .operands_out(vec![a]),
-    );
-
     let BoolTo = &TypeVar::new(
         "BoolTo",
         "A larger boolean type",

cranelift/codegen/src/isa/aarch64/lower.isle

@@ -1653,7 +1653,7 @@
 (rule (lower (has_type (ty_vec128 ty) (vselect c x y)))
         (bsl ty c x y))
 
-;;;; Rules for `ireduce` / `breduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;;; Rules for `ireduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; T -> I{64,32,16,8}: We can simply pass through the value: values
 ;; are always stored with high bits undefined, so we can just leave
@@ -1662,13 +1662,6 @@
     (if (ty_int_bool_ref_scalar_64 ty))
     (value_regs_get src 0))
 
-;; Likewise for breduce.
-
-(rule (lower (has_type ty (breduce src)))
-      (if (ty_int_bool_ref_scalar_64 ty))
-      (value_regs_get src 0))
-
-
 ;;;; Rules for `fcmp` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (rule 4 (lower (has_type ty @ (multi_lane _ _) (fcmp (fcmp_zero_cond_not_eq cond) x y)))

cranelift/codegen/src/isa/aarch64/lower_inst.rs

@@ -148,7 +148,7 @@ pub(crate) fn lower_insn_to_regs(
 
         Opcode::Copy => implemented_in_isle(ctx),
 
-        Opcode::Breduce | Opcode::Ireduce => implemented_in_isle(ctx),
+        Opcode::Ireduce => implemented_in_isle(ctx),
 
         Opcode::Bextend | Opcode::Bmask => implemented_in_isle(ctx),
 

cranelift/codegen/src/isa/riscv64/lower.isle

@@ -539,11 +539,6 @@
 (rule (lower (has_type ty (copy x)))
   (gen_move2 x ty ty))
 
-;;;;;  Rules for `breduce`;;;;;;;;;;;;;;;;;
-(rule
-  (lower (has_type ty (breduce x)))
-  (gen_move2 (value_regs_get x 0) ty ty))
-
 ;;;;;  Rules for `ireduce`;;;;;;;;;;;;;;;;;
 (rule
   (lower (has_type ty (ireduce x)))

cranelift/codegen/src/isa/s390x/lower.isle

@@ -1155,17 +1155,6 @@
       (vec_select ty y z x))
 
 
-;;;; Rules for `breduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; Up to 64-bit source type: Always a no-op.
-(rule 1 (lower (breduce x @ (value_type (fits_in_64 _ty))))
-      x)
-
-;; 128-bit source type: Extract the low half.
-(rule (lower (breduce x @ (value_type (vr128_ty _ty))))
-      (vec_extract_lane $I64X2 x 1 (zero_reg)))
-
-
 ;;;; Rules for `bextend` and `bmask` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; Use a common helper to type cast bools to either bool or integer types.

cranelift/codegen/src/isa/s390x/lower.rs

@@ -99,7 +99,6 @@ impl LowerBackend for S390xBackend {
             | Opcode::BxorNot
             | Opcode::Bitselect
             | Opcode::Vselect
-            | Opcode::Breduce
             | Opcode::Bextend
             | Opcode::Bmask
             | Opcode::Bint

cranelift/codegen/src/isa/x64/lower.isle

@@ -2108,7 +2108,7 @@
                  (bextend src @ (value_type src_ty))))
       (generic_sextend src src_ty dst_ty))
 
-;; Rules for `ireduce` / `breduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Rules for `ireduce` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; T -> T is always a no-op, even I128 -> I128.
 (rule (lower (has_type ty (ireduce src @ (value_type ty))))
@@ -2120,14 +2120,6 @@
 (rule 1 (lower (has_type (fits_in_64 ty) (ireduce src)))
       (value_regs_get_gpr src 0))
 
-;; Likewise for breduce.
-
-(rule (lower (has_type ty (breduce src @ (value_type ty))))
-      src)
-
-(rule 1 (lower (has_type (fits_in_64 ty) (breduce src)))
-      (value_regs_get_gpr src 0))
-
 ;; Rules for `bint` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ;; Booleans are stored as all-zeroes (0) or all-ones (-1). We AND out

cranelift/codegen/src/isa/x64/lower.rs

@@ -367,7 +367,6 @@ fn lower_insn_to_regs(
         | Opcode::IsInvalid
         | Opcode::Uextend
         | Opcode::Sextend
-        | Opcode::Breduce
         | Opcode::Bextend
         | Opcode::Ireduce
         | Opcode::Bint

cranelift/codegen/src/verifier/mod.rs

@@ -1535,28 +1535,6 @@ impl<'a> Verifier<'a> {
                             ));
                         }
                     }
-                    Opcode::Breduce | Opcode::Ireduce | Opcode::Fdemote => {
-                        if arg_type.lane_count() != ctrl_type.lane_count() {
-                            return errors.nonfatal((
-                                inst,
-                                self.context(inst),
-                                format!(
-                                    "input {} and output {} must have same number of lanes",
-                                    arg_type, ctrl_type,
-                                ),
-                            ));
-                        }
-                        if arg_type.lane_bits() <= ctrl_type.lane_bits() {
-                            return errors.nonfatal((
-                                inst,
-                                self.context(inst),
-                                format!(
-                                    "input {} must be larger than output {}",
-                                    arg_type, ctrl_type,
-                                ),
-                            ));
-                        }
-                    }
                     _ => {}
                 }
             }

cranelift/filetests/filetests/isa/aarch64/simd.clif

@@ -28,19 +28,6 @@ block0:
 ;   dup v0.8h, w2
 ;   ret
 
-function %f3() -> i8x16 {
-block0:
-  v0 = iconst.i32 -1
-  v1 = breduce.i8 v0
-  v2 = splat.i8x16 v1
-  return v2
-}
-
-; block0:
-;   movn x2, #0
-;   dup v0.16b, w2
-;   ret
-
 function %f4(i32, i8x16, i8x16) -> i8x16 {
 block0(v0: i32, v1: i8x16, v2: i8x16):
    v3 = select v0, v1, v2

cranelift/filetests/filetests/isa/s390x/conversions.clif

@@ -481,151 +481,6 @@ block0(v0: i8):
 ;   srak %r2, %r5, 31
 ;   br %r14
 
-function %breduce_i128_i64(i128) -> i64 {
-block0(v0: i128):
-  v1 = breduce.i64 v0
-  return v1
-}
-
-; block0:
-;   vl %v0, 0(%r2)
-;   vlgvg %r2, %v0, 1
-;   br %r14
-
-function %breduce_i128_i32(i128) -> i32 {
-block0(v0: i128):
-  v1 = breduce.i32 v0
-  return v1
-}
-
-; block0:
-;   vl %v0, 0(%r2)
-;   vlgvg %r2, %v0, 1
-;   br %r14
-
-function %breduce_i128_i16(i128) -> i16 {
-block0(v0: i128):
-  v1 = breduce.i16 v0
-  return v1
-}
-
-; block0:
-;   vl %v0, 0(%r2)
-;   vlgvg %r2, %v0, 1
-;   br %r14
-
-function %breduce_i128_i8(i128) -> i8 {
-block0(v0: i128):
-  v1 = breduce.i8 v0
-  return v1
-}
-
-; block0:
-;   vl %v0, 0(%r2)
-;   vlgvg %r2, %v0, 1
-;   br %r14
-
-function %breduce_i128_i8(i128) -> i8 {
-block0(v0: i128):
-  v1 = breduce.i8 v0
-  return v1
-}
-
-; block0:
-;   vl %v0, 0(%r2)
-;   vlgvg %r2, %v0, 1
-;   br %r14
-
-function %breduce_i64_i32(i64, i64) -> i32 {
-block0(v0: i64, v1: i64):
-  v2 = breduce.i32 v1
-  return v2
-}
-
-; block0:
-;   lgr %r2, %r3
-;   br %r14
-
-function %breduce_i64_i16(i64, i64) -> i16 {
-block0(v0: i64, v1: i64):
-  v2 = breduce.i16 v1
-  return v2
-}
-
-; block0:
-;   lgr %r2, %r3
-;   br %r14
-
-function %breduce_i64_i8(i64, i64) -> i8 {
-block0(v0: i64, v1: i64):
-  v2 = breduce.i8 v1
-  return v2
-}
-
-; block0:
-;   lgr %r2, %r3
-;   br %r14
-
-function %breduce_i64_i8(i64, i64) -> i8 {
-block0(v0: i64, v1: i64):
-  v2 = breduce.i8 v1
-  return v2
-}
-
-; block0:
-;   lgr %r2, %r3
-;   br %r14
-
-function %breduce_i32_i16(i32, i32) -> i16 {
-block0(v0: i32, v1: i32):
-  v2 = breduce.i16 v1
-  return v2
-}
-
-; block0:
-;   lgr %r2, %r3
-;   br %r14
-
-function %breduce_i32_i8(i32, i32) -> i8 {
-block0(v0: i32, v1: i32):
-  v2 = breduce.i8 v1
-  return v2
-}
-
-; block0:
-;   lgr %r2, %r3
-;   br %r14
-
-function %breduce_i32_i8(i32, i32) -> i8 {
-block0(v0: i32, v1: i32):
-  v2 = breduce.i8 v1
-  return v2
-}
-
-; block0:
-;   lgr %r2, %r3
-;   br %r14
-
-function %breduce_i16_i8(i16, i16) -> i8 {
-block0(v0: i16, v1: i16):
-  v2 = breduce.i8 v1
-  return v2
-}
-
-; block0:
-;   lgr %r2, %r3
-;   br %r14
-
-function %breduce_i16_i8(i16, i16) -> i8 {
-block0(v0: i16, v1: i16):
-  v2 = breduce.i8 v1
-  return v2
-}
-
-; block0:
-;   lgr %r2, %r3
-;   br %r14
-
 function %bmask_i128_i128(i128) -> i128 {
 block0(v0: i128):
   v1 = bmask.i128 v0