riscv64: Implement insertlane (#6408)

* riscv64: Support vector instruction masking * riscv64: Add `vmerge` instructions * riscv64: Implement `insertlane` * riscv64: Fix encoding of `vmv` instructions Some of these carry their source in vs2 * riscv64: Fix formatting of mask register Remove the space between , and the register. This is inline with the rest of our formatting. * riscv64: Restrict `insertlane` to vector types that fit in a single register * wasmtime: Enable more RISC-V SIMD tests * riscv64: Use inline format syntax for printing vector instructions * riscv64: Add vector mask note
bytecodealliance · May 20, 2023 · 9871098 · 9871098
1 parent 28931a4
commit 9871098
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Showing 10 changed files with 1,007 additions and 196 deletions.
diff --git a/build.rs b/build.rs
@@ -210,7 +210,6 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
                 "issue4807",
                 "issue_3327_bnot_lowering",
                 "load_splat_out_of_bounds",
-                "replace_lane_preserve",
                 "simd_align",
                 "simd_bit_shift",
                 "simd_bitwise",
@@ -246,10 +245,6 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
                 "simd_int_to_int_extend",
                 "simd_lane",
                 "simd_load",
-                "simd_load16_lane",
-                "simd_load32_lane",
-                "simd_load64_lane",
-                "simd_load8_lane",
                 "simd_load_extend",
                 "simd_load_zero",
                 "simd_splat",

diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle
@@ -328,25 +328,29 @@
       (vd WritableReg)
       (vs2 Reg)
       (vs1 Reg)
+      (mask VecOpMasking)
       (vstate VState))
 
     (VecAluRRImm5
       (op VecAluOpRRImm5)
       (vd WritableReg)
       (vs2 Reg)
       (imm Imm5)
+      (mask VecOpMasking)
       (vstate VState))
 
     (VecAluRR
       (op VecAluOpRR)
       (vd WritableReg)
       (vs Reg)
+      (mask VecOpMasking)
       (vstate VState))
 
     (VecAluRImm5
       (op VecAluOpRImm5)
       (vd WritableReg)
       (imm Imm5)
+      (mask VecOpMasking)
       (vstate VState))
 
     (VecSetState
@@ -358,13 +362,15 @@
       (to WritableReg)
       (from VecAMode)
       (flags MemFlags)
+      (mask VecOpMasking)
       (vstate VState))
 
     (VecStore
       (eew VecElementWidth)
       (to VecAMode)
       (from Reg)
       (flags MemFlags)
+      (mask VecOpMasking)
       (vstate VState))
 ))
 

diff --git a/cranelift/codegen/src/isa/riscv64/inst/emit.rs b/cranelift/codegen/src/isa/riscv64/inst/emit.rs
@@ -5,7 +5,6 @@ use crate::ir::RelSourceLoc;
 use crate::ir::TrapCode;
 use crate::isa::riscv64::inst::*;
 use crate::isa::riscv64::inst::{zero_reg, AluOPRRR};
-use crate::isa::riscv64::lower::isle::generated_code::VecOpMasking;
 use crate::machinst::{AllocationConsumer, Reg, Writable};
 use cranelift_control::ControlPlane;
 use regalloc2::Allocation;
@@ -2804,32 +2803,58 @@ impl MachInstEmit for Inst {
                 sink.bind_label(label_done, &mut state.ctrl_plane);
             }
             &Inst::VecAluRRR {
-                op, vd, vs1, vs2, ..
+                op,
+                vd,
+                vs1,
+                vs2,
+                ref mask,
+                ..
             } => {
                 let vs1 = allocs.next(vs1);
                 let vs2 = allocs.next(vs2);
                 let vd = allocs.next_writable(vd);
+                let mask = mask.with_allocs(&mut allocs);
 
-                sink.put4(encode_valu(op, vd, vs1, vs2, VecOpMasking::Disabled));
+                sink.put4(encode_valu(op, vd, vs1, vs2, mask));
             }
             &Inst::VecAluRRImm5 {
-                op, vd, imm, vs2, ..
+                op,
+                vd,
+                imm,
+                vs2,
+                ref mask,
+                ..
             } => {
                 let vs2 = allocs.next(vs2);
                 let vd = allocs.next_writable(vd);
+                let mask = mask.with_allocs(&mut allocs);
 
-                sink.put4(encode_valu_imm(op, vd, imm, vs2, VecOpMasking::Disabled));
+                sink.put4(encode_valu_imm(op, vd, imm, vs2, mask));
             }
-            &Inst::VecAluRR { op, vd, vs, .. } => {
+            &Inst::VecAluRR {
+                op,
+                vd,
+                vs,
+                ref mask,
+                ..
+            } => {
                 let vs = allocs.next(vs);
                 let vd = allocs.next_writable(vd);
+                let mask = mask.with_allocs(&mut allocs);
 
-                sink.put4(encode_valu_rr(op, vd, vs, VecOpMasking::Disabled));
+                sink.put4(encode_valu_rr(op, vd, vs, mask));
             }
-            &Inst::VecAluRImm5 { op, vd, imm, .. } => {
+            &Inst::VecAluRImm5 {
+                op,
+                vd,
+                imm,
+                ref mask,
+                ..
+            } => {
                 let vd = allocs.next_writable(vd);
+                let mask = mask.with_allocs(&mut allocs);
 
-                sink.put4(encode_valu_r_imm(op, vd, imm, VecOpMasking::Disabled));
+                sink.put4(encode_valu_r_imm(op, vd, imm, mask));
             }
             &Inst::VecSetState { rd, ref vstate } => {
                 let rd = allocs.next_writable(rd);
@@ -2849,11 +2874,13 @@ impl MachInstEmit for Inst {
                 eew,
                 to,
                 ref from,
+                ref mask,
                 flags,
                 ..
             } => {
                 let from = from.clone().with_allocs(&mut allocs);
                 let to = allocs.next_writable(to);
+                let mask = mask.with_allocs(&mut allocs);
 
                 // Vector Loads don't support immediate offsets, so we need to load it into a register.
                 let addr = match from {
@@ -2889,8 +2916,7 @@ impl MachInstEmit for Inst {
                     eew,
                     addr,
                     from.lumop(),
-                    // We don't implement masking yet.
-                    VecOpMasking::Disabled,
+                    mask,
                     from.mop(),
                     from.nf(),
                 ));
@@ -2900,11 +2926,13 @@ impl MachInstEmit for Inst {
                 eew,
                 ref to,
                 from,
+                ref mask,
                 flags,
                 ..
             } => {
                 let to = to.clone().with_allocs(&mut allocs);
                 let from = allocs.next(from);
+                let mask = mask.with_allocs(&mut allocs);
 
                 // Vector Stores don't support immediate offsets, so we need to load it into a register.
                 let addr = match to {
@@ -2940,8 +2968,7 @@ impl MachInstEmit for Inst {
                     eew,
                     addr,
                     to.sumop(),
-                    // We don't implement masking yet.
-                    VecOpMasking::Disabled,
+                    mask,
                     to.mop(),
                     to.nf(),
                 ));