cranelift: Port trap and resumable_trap lowering to ISLE on x64

bytecodealliance · Jan 13, 2022 · 658c5d3 · 658c5d3
1 parent 5bb3645
commit 658c5d3
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Showing 9 changed files with 299 additions and 185 deletions.
diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest
@@ -1,4 +1,4 @@
 src/clif.isle f176ef3bba99365
-src/prelude.isle 7b911d3b894ae17
+src/prelude.isle 181213982a49a4b8
 src/isa/aarch64/inst.isle 5fa80451697b084f
 src/isa/aarch64/lower.isle 2d2e1e076a0c8a23
diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs
diff --git a/cranelift/codegen/src/isa/x64/inst.isle b/cranelift/codegen/src/isa/x64/inst.isle
@@ -4,6 +4,7 @@
 
 (type MInst extern
       (enum (Nop (len u8))
+            (Ud2 (trap_code TrapCode))
             (AluRmiR (size OperandSize)
                      (op AluRmiROpcode)
                      (src1 Reg)
@@ -1444,3 +1445,8 @@
       (let ((dst WritableReg (temp_writable_reg $I64))
             (_ Unit (emit (MInst.LoadEffectiveAddress addr dst))))
         (writable_reg_to_reg dst)))
+
+;; Helper for creating `ud2` instructions.
+(decl ud2 (TrapCode) SideEffectNoResult)
+(rule (ud2 code)
+      (SideEffectNoResult.Inst (MInst.Ud2 code)))
diff --git a/cranelift/codegen/src/isa/x64/lower.isle b/cranelift/codegen/src/isa/x64/lower.isle
@@ -1432,3 +1432,13 @@
 
 (rule (lower (has_type $I32X4 (umin x y)))
       (value_reg (pminud (put_in_reg x) (put_in_reg_mem y))))
+
+;;;; Rules for `trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (trap code))
+      (value_regs_none (ud2 code)))
+
+;;;; Rules for `resumable_trap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (resumable_trap code))
+      (value_regs_none (ud2 code)))
diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
@@ -1234,7 +1234,9 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
         | Opcode::Ishl
         | Opcode::Rotl
         | Opcode::Rotr
-        | Opcode::Ineg => implemented_in_isle(ctx),
+        | Opcode::Ineg
+        | Opcode::Trap
+        | Opcode::ResumableTrap => implemented_in_isle(ctx),
 
         Opcode::Clz => {
             let orig_ty = ty.unwrap();
@@ -2369,11 +2371,6 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             ctx.emit(Inst::Hlt);
         }
 
-        Opcode::Trap | Opcode::ResumableTrap => {
-            let trap_code = ctx.data(insn).trap_code().unwrap();
-            ctx.emit_safepoint(Inst::Ud2 { trap_code });
-        }
-
         Opcode::Trapif | Opcode::Trapff => {
             let trap_code = ctx.data(insn).trap_code().unwrap();
 

diff --git a/cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest b/cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest
@@ -1,4 +1,4 @@
 src/clif.isle f176ef3bba99365
-src/prelude.isle 7b911d3b894ae17
-src/isa/x64/inst.isle 755420ee1a9c7aeb
-src/isa/x64/lower.isle 38ddbc7b4a8444cf
+src/prelude.isle 181213982a49a4b8
+src/isa/x64/inst.isle 61004acbb1289816
+src/isa/x64/lower.isle 82db7f7d47ac7809