ISLE: Rename {gpr,xmm}_mem_new constructors to `reg_mem_to_{gpr,xmm…

…}_mem`

cranelift/codegen/src/isa/x64/inst.isle

@@ -876,8 +876,8 @@
 ;; Construct a new `XmmMem` from the given `RegMem`.
 ;;
 ;; Asserts that the `RegMem`'s register, if any, is an XMM register.
-(decl xmm_mem_new (RegMem) XmmMem)
-(extern constructor xmm_mem_new xmm_mem_new)
+(decl reg_mem_to_xmm_mem (RegMem) XmmMem)
+(extern constructor reg_mem_to_xmm_mem reg_mem_to_xmm_mem)
 
 ;; Construct a new `GprMemImm` from the given `RegMemImm`.
 ;;
@@ -918,8 +918,8 @@
 ;; Construct a new `GprMem` from a `RegMem`.
 ;;
 ;; Asserts that the `RegMem`'s register, if any, is a GPR.
-(decl gpr_mem_new (RegMem) GprMem)
-(extern constructor gpr_mem_new gpr_mem_new)
+(decl reg_mem_to_gpr_mem (RegMem) GprMem)
+(extern constructor reg_mem_to_gpr_mem reg_mem_to_gpr_mem)
 
 ;; Construct a `GprMem` from a `Reg`.
 ;;
@@ -939,7 +939,7 @@
 ;; Asserts that the value goes into a GPR.
 (decl put_in_gpr_mem (Value) GprMem)
 (rule (put_in_gpr_mem val)
-      (gpr_mem_new (put_in_reg_mem val)))
+      (reg_mem_to_gpr_mem (put_in_reg_mem val)))
 
 ;; Put a value into a `GprMemImm`.
 ;;
@@ -960,7 +960,7 @@
 ;; Asserts that the value goes into a XMM.
 (decl put_in_xmm_mem (Value) XmmMem)
 (rule (put_in_xmm_mem val)
-      (xmm_mem_new (put_in_reg_mem val)))
+      (reg_mem_to_xmm_mem (put_in_reg_mem val)))
 
 ;; Put a value into a `XmmMemImm`.
 ;;
@@ -1177,23 +1177,23 @@
 
 (rule (x64_load $F32 addr _ext_kind)
       (xmm_to_reg (xmm_unary_rm_r (SseOpcode.Movss)
-                                  (xmm_mem_new (synthetic_amode_to_reg_mem addr)))))
+                                  (reg_mem_to_xmm_mem (synthetic_amode_to_reg_mem addr)))))
 
 (rule (x64_load $F64 addr _ext_kind)
       (xmm_to_reg (xmm_unary_rm_r (SseOpcode.Movsd)
-                                  (xmm_mem_new (synthetic_amode_to_reg_mem addr)))))
+                                  (reg_mem_to_xmm_mem (synthetic_amode_to_reg_mem addr)))))
 
 (rule (x64_load $F32X4 addr _ext_kind)
       (xmm_to_reg (xmm_unary_rm_r (SseOpcode.Movups)
-                                  (xmm_mem_new (synthetic_amode_to_reg_mem addr)))))
+                                  (reg_mem_to_xmm_mem (synthetic_amode_to_reg_mem addr)))))
 
 (rule (x64_load $F64X2 addr _ext_kind)
       (xmm_to_reg (xmm_unary_rm_r (SseOpcode.Movupd)
-                                  (xmm_mem_new (synthetic_amode_to_reg_mem addr)))))
+                                  (reg_mem_to_xmm_mem (synthetic_amode_to_reg_mem addr)))))
 
 (rule (x64_load (multi_lane _bits _lanes) addr _ext_kind)
       (xmm_to_reg (xmm_unary_rm_r (SseOpcode.Movdqu)
-                                  (xmm_mem_new (synthetic_amode_to_reg_mem addr)))))
+                                  (reg_mem_to_xmm_mem (synthetic_amode_to_reg_mem addr)))))
 
 ;;;; Instruction Constructors ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
@@ -1317,13 +1317,13 @@
 ;; `f32` immediates.
 (rule (imm $F32 bits)
       (xmm_to_reg (gpr_to_xmm (SseOpcode.Movd)
-                              (gpr_mem_new (RegMem.Reg (imm $I32 bits)))
+                              (reg_mem_to_gpr_mem (RegMem.Reg (imm $I32 bits)))
                               (OperandSize.Size32))))
 
 ;; `f64` immediates.
 (rule (imm $F64 bits)
       (xmm_to_reg (gpr_to_xmm (SseOpcode.Movq)
-                              (gpr_mem_new (RegMem.Reg (imm $I64 bits)))
+                              (reg_mem_to_gpr_mem (RegMem.Reg (imm $I64 bits)))
                               (OperandSize.Size64))))
 
 (decl nonzero_u64_fits_in_u32 (u64) u64)

cranelift/codegen/src/isa/x64/lower.isle

@@ -591,7 +591,7 @@
             (unmasked Xmm (psllw src_ amt_xmm))
             (mask_addr SyntheticAmode (ishl_i8x16_mask amt_gpr))
             (mask Reg (x64_load $I8X16 mask_addr (ExtKind.None))))
-        (value_xmm (sse_and $I8X16 unmasked (xmm_mem_new (RegMem.Reg mask))))))
+        (value_xmm (sse_and $I8X16 unmasked (reg_mem_to_xmm_mem (RegMem.Reg mask))))))
 
 ;; Get the address of the mask to use when fixing up the lanes that weren't
 ;; correctly generated by the 16x8 shift.
@@ -690,7 +690,7 @@
             (mask Reg (x64_load $I8X16 mask_addr (ExtKind.None))))
         (value_xmm (sse_and $I8X16
                             unmasked
-                            (xmm_mem_new (RegMem.Reg mask))))))
+                            (reg_mem_to_xmm_mem (RegMem.Reg mask))))))
 
 ;; Get the address of the mask to use when fixing up the lanes that weren't
 ;; correctly generated by the 16x8 shift.
@@ -837,8 +837,8 @@
             (amt_ Imm8Reg (put_masked_in_imm8_reg amt $I64))
             (shifted_lo Reg (sar $I64 (gpr_to_reg lo) amt_))
             (shifted_hi Reg (sar $I64 (gpr_to_reg hi) amt_)))
-        (value_xmm (make_i64x2_from_lanes (gpr_mem_new (RegMem.Reg shifted_lo))
-                                          (gpr_mem_new (RegMem.Reg shifted_hi))))))
+        (value_xmm (make_i64x2_from_lanes (reg_mem_to_gpr_mem (RegMem.Reg shifted_lo))
+                                          (reg_mem_to_gpr_mem (RegMem.Reg shifted_hi))))))
 
 ;;;; Rules for `rotl` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
@@ -1363,23 +1363,23 @@
 
 ;; i8x16.replace_lane
 (rule (vec_insert_lane $I8X16 vec val idx)
-      (pinsrb vec (gpr_mem_new val) idx))
+      (pinsrb vec (reg_mem_to_gpr_mem val) idx))
 
 ;; i16x8.replace_lane
 (rule (vec_insert_lane $I16X8 vec val idx)
-      (pinsrw vec (gpr_mem_new val) idx))
+      (pinsrw vec (reg_mem_to_gpr_mem val) idx))
 
 ;; i32x4.replace_lane
 (rule (vec_insert_lane $I32X4 vec val idx)
-      (pinsrd vec (gpr_mem_new val) idx (OperandSize.Size32)))
+      (pinsrd vec (reg_mem_to_gpr_mem val) idx (OperandSize.Size32)))
 
 ;; i64x2.replace_lane
 (rule (vec_insert_lane $I64X2 vec val idx)
-      (pinsrd vec (gpr_mem_new val) idx (OperandSize.Size64)))
+      (pinsrd vec (reg_mem_to_gpr_mem val) idx (OperandSize.Size64)))
 
 ;; f32x4.replace_lane
 (rule (vec_insert_lane $F32X4 vec val idx)
-      (insertps vec (xmm_mem_new val) (sse_insertps_lane_imm idx)))
+      (insertps vec (reg_mem_to_xmm_mem val) (sse_insertps_lane_imm idx)))
 
 ;; External rust code used to calculate the immediate value to `insertps`.
 (decl sse_insertps_lane_imm (u8) u8)
@@ -1401,18 +1401,18 @@
 ;; internally as `xmm_rm_r` will merge the temp register into our `vec`
 ;; register.
 (rule (vec_insert_lane $F64X2 vec (RegMem.Reg val) 0)
-      (movsd vec (xmm_mem_new (RegMem.Reg val))))
+      (movsd vec (reg_mem_to_xmm_mem (RegMem.Reg val))))
 (rule (vec_insert_lane $F64X2 vec mem 0)
       (movsd vec (xmm_to_xmm_mem (xmm_unary_rm_r (SseOpcode.Movsd)
-                                                 (xmm_mem_new mem)))))
+                                                 (reg_mem_to_xmm_mem mem)))))
 
 ;; f64x2.replace_lane 1
 ;;
 ;; Here the `movlhps` instruction is used specifically to specialize moving
 ;; into the second lane where unlike above cases we're not using the lane
 ;; immediate as an immediate to the instruction itself.
 (rule (vec_insert_lane $F64X2 vec val 1)
-      (movlhps vec (xmm_mem_new val)))
+      (movlhps vec (reg_mem_to_xmm_mem val)))
 
 ;;;; Rules for `imax` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 

cranelift/codegen/src/isa/x64/lower/isle.rs

@@ -360,7 +360,7 @@ where
     }
 
     #[inline]
-    fn xmm_mem_new(&mut self, rm: &RegMem) -> XmmMem {
+    fn reg_mem_to_xmm_mem(&mut self, rm: &RegMem) -> XmmMem {
         XmmMem::new(rm.clone()).unwrap()
     }
 
@@ -400,7 +400,7 @@ where
     }
 
     #[inline]
-    fn gpr_mem_new(&mut self, rm: &RegMem) -> GprMem {
+    fn reg_mem_to_gpr_mem(&mut self, rm: &RegMem) -> GprMem {
         GprMem::new(rm.clone()).unwrap()
     }
 

cranelift/codegen/src/isa/x64/lower/isle/generated_code.manifest

@@ -1,4 +1,4 @@
 src/clif.isle 9ea75a6f790b5c03
 src/prelude.isle 6aaf8ce0f5a5c2ec
-src/isa/x64/inst.isle 2f76eb1f9ecf0c5e
-src/isa/x64/lower.isle 144c33c4e64a17a7
+src/isa/x64/inst.isle 7513533d16948249
+src/isa/x64/lower.isle ccda13e9fe83c89a