Fix some typos (#8641)

* occurred

* winch typos

* tests typos

* cli typos

* fuzz typos

* examples typos

* docs typos

* crates/wasmtime typos

* crates/environ typos

* crates/cranelift typos

* crates/test-programs typos

* crates/c-api typos

* crates/cache typos

* crates other typos

* cranelift/codegen/src/isa typos

* cranelift/codegen/src other typos

* cranelift/codegen other typos

* cranelift other typos

* ci js typo

* .github workflows typo

* RELEASES typo

* Fix clang-format documentation line

---------

Co-authored-by: Andrew Brown <andrew.brown@intel.com>

.github/workflows/main.yml

@@ -725,7 +725,7 @@ jobs:
     - run: rustup target add wasm32-wasi wasm32-unknown-unknown
     - run: |
         sudo apt-get update && sudo apt-get install -y gdb lldb-15 llvm
-        # woraround for https://bugs.launchpad.net/ubuntu/+source/llvm-defaults/+bug/1972855
+        # workaround for https://bugs.launchpad.net/ubuntu/+source/llvm-defaults/+bug/1972855
         sudo mkdir -p /usr/lib/local/lib/python3.10/dist-packages/lldb
         sudo ln -s /usr/lib/llvm-15/lib/python3.10/dist-packages/lldb/* /usr/lib/python3/dist-packages/lldb/
         cargo test test_debug_dwarf -- --ignored --test-threads 1

RELEASES.md

@@ -2815,7 +2815,7 @@ Released 2022-03-07.
   [#3837](https://github.com/bytecodealliance/wasmtime/pull/3837)
 
 * The native stack size allowed for WebAssembly has been decreased from 1 MiB to
-  512 KiB on all platforms to better accomodate running wasm on the main thread
+  512 KiB on all platforms to better accommodate running wasm on the main thread
   on Windows.
   [#3861](https://github.com/bytecodealliance/wasmtime/pull/3861)
 
@@ -3300,7 +3300,7 @@ Released 2021-05-21.
 
 ### Added
 
-* Support for IBM z/Archiecture (`s390x`) machines in Cranelift and Wasmtime:
+* Support for IBM z/Architecture (`s390x`) machines in Cranelift and Wasmtime:
   [#2836](https://github.com/bytecodealliance/wasmtime/pull/2836),
   [#2837](https://github.com/bytecodealliance/wasmtime/pull/2837),
   [#2838](https://github.com/bytecodealliance/wasmtime/pull/2838),
@@ -3849,7 +3849,7 @@ is now enabled by default.
 
   [#1667](https://github.com/bytecodealliance/wasmtime/pull/1667)
 
-The Rust API does not require a store provided during `Module::new` operation. The `Module` can be send accross threads and instantiate for a specific store. The `Instance::new` now requires the store.
+The Rust API does not require a store provided during `Module::new` operation. The `Module` can be send across threads and instantiate for a specific store. The `Instance::new` now requires the store.
 
   [#1761](https://github.com/bytecodealliance/wasmtime/pull/1761)
 

ci/build-test-matrix.js

@@ -151,9 +151,9 @@ async function getWorkspaceMembers() {
 /// buckets across that config.
 ///
 /// This is essentially a `flat_map` where each config that logically tests all
-/// crates int he workspace is mapped to N sharded configs that each test only a
+/// crates in the workspace is mapped to N sharded configs that each test only a
 /// subset of crates in the workspace. Each sharded config's subset of crates to
-/// test are disjoint from all its siblings, and the union of all thes siblings'
+/// test are disjoint from all its siblings, and the union of all these siblings'
 /// crates to test is the full workspace members set.
 ///
 /// With some poetic license around a `crates_to_test` key that doesn't actually

cranelift/codegen/Cargo.toml

@@ -38,7 +38,7 @@ rustc-hash  = { workspace = true }
 # It is a goal of the cranelift-codegen crate to have minimal external dependencies.
 # Please don't add any unless they are essential to the task of creating binary
 # machine code. Integration tests that need external dependencies can be
-# accomodated in `tests`.
+# accommodated in `tests`.
 
 [dev-dependencies]
 criterion = { workspace = true }

cranelift/codegen/meta/src/cdsl/types.rs

@@ -185,15 +185,15 @@ impl LaneType {
             32 => shared_types::Int::I32,
             64 => shared_types::Int::I64,
             128 => shared_types::Int::I128,
-            _ => unreachable!("unxpected num bits for int"),
+            _ => unreachable!("unexpected num bits for int"),
         })
     }
 
     pub fn float_from_bits(num_bits: u16) -> LaneType {
         LaneType::Float(match num_bits {
             32 => shared_types::Float::F32,
             64 => shared_types::Float::F64,
-            _ => unreachable!("unxpected num bits for float"),
+            _ => unreachable!("unexpected num bits for float"),
         })
     }
 

cranelift/codegen/meta/src/isa/riscv64.rs

@@ -141,7 +141,7 @@ pub(crate) fn define() -> TargetIsa {
     );
 
     // Zvl*: Minimum Vector Length Standard Extensions
-    // These extension specifiy the minimum number of bits in a vector register.
+    // These extension specify the minimum number of bits in a vector register.
     // Since it is a minimum, Zvl64b implies Zvl32b, Zvl128b implies Zvl64b, etc.
     // The V extension supports a maximum of 64K bits in a single register.
     //

cranelift/codegen/shared/src/constants.rs

@@ -13,7 +13,7 @@
 // Vector types are encoded with the lane type in the low 4 bits and log2(lanes)
 // in the next highest 4 bits, giving a range of 2-256 lanes.
 
-// Dynamic vector types are encoded similarily.
+// Dynamic vector types are encoded similarly.
 
 /// Start of the lane types.
 pub const LANE_BASE: u16 = 0x70;

cranelift/codegen/src/ir/dfg.rs

@@ -656,7 +656,7 @@ fn encode_narrow_field(x: u32, bits: u8) -> u32 {
         debug_assert!(
             x < max,
             "{x} does not fit into {bits} bits (must be less than {max} to \
-             allow for a 0xffffffff sentinal)"
+             allow for a 0xffffffff sentinel)"
         );
         x
     }

cranelift/codegen/src/ir/immediates.rs

@@ -754,7 +754,7 @@ impl Ieee32 {
     }
 
     /// Create an `Ieee32` number representing the greatest negative value
-    /// not convertable from f32 to a signed integer with width n.
+    /// not convertible from f32 to a signed integer with width n.
     pub fn fcvt_to_sint_negative_overflow<I: Into<i32>>(n: I) -> Self {
         let n = n.into();
         debug_assert!(n < 32);
@@ -971,7 +971,7 @@ impl Ieee64 {
     }
 
     /// Create an `Ieee64` number representing the greatest negative value
-    /// not convertable from f64 to a signed integer with width n.
+    /// not convertible from f64 to a signed integer with width n.
     pub fn fcvt_to_sint_negative_overflow<I: Into<i64>>(n: I) -> Self {
         let n = n.into();
         debug_assert!(n < 64);

cranelift/codegen/src/isa/aarch64/abi.rs

@@ -215,7 +215,7 @@ impl ABIMachineSpec for AArch64MachineDeps {
             //
             // See AArch64 ABI (https://github.com/ARM-software/abi-aa/blob/2021Q1/aapcs64/aapcs64.rst#642parameter-passing-rules), (Section 6.4.2 Stage C).
             //
-            // For arguments with alignment of 16 we round up the the register number
+            // For arguments with alignment of 16 we round up the register number
             // to the next even value. So we can never allocate for example an i128
             // to X1 and X2, we have to skip one register and do X2, X3
             // (Stage C.8)

cranelift/codegen/src/isa/aarch64/inst.isle

@@ -185,7 +185,7 @@
         (size OperandSize))
 
        ;; A MOVK with a 16-bit immediate. Modifies its register; we
-       ;; model this with a seprate input `rn` and output `rd` virtual
+       ;; model this with a separate input `rn` and output `rd` virtual
        ;; register, with a regalloc constraint to tie them together.
        (MovK
         (rd WritableReg)
@@ -1700,7 +1700,7 @@
 (decl use_lse () Inst)
 (extern extractor use_lse use_lse)
 
-;; Extractor helpers for various immmediate constants ;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Extractor helpers for various immediate constants ;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 (decl pure partial move_wide_const_from_u64 (Type u64) MoveWideConst)
 (extern constructor move_wide_const_from_u64 move_wide_const_from_u64)

cranelift/codegen/src/isa/aarch64/inst/args.rs

@@ -14,7 +14,7 @@ pub enum ShiftOp {
     LSL = 0b00,
     /// Logical shift right.
     LSR = 0b01,
-    /// Arithmentic shift right.
+    /// Arithmetic shift right.
     ASR = 0b10,
     /// Rotate right.
     ROR = 0b11,

cranelift/codegen/src/isa/aarch64/inst/emit.rs

@@ -1061,7 +1061,7 @@ impl MachInstEmit for Inst {
                             &Inst::FpuLoad128 { .. } => {
                                 sink.put4(enc_ldst_imm19(0b10011100, offset, rd));
                             }
-                            _ => panic!("Unspported size for LDR from constant pool!"),
+                            _ => panic!("Unsupported size for LDR from constant pool!"),
                         }
                     }
                     &AMode::SPPreIndexed { simm9 } => {

cranelift/codegen/src/isa/aarch64/inst/imms.rs

@@ -178,7 +178,7 @@ impl FPURightShiftImm {
         // | 32                | 01xxxxx  |
         // | 64                | 1xxxxxx  |
         //
-        // The shift amount is negated such that a shift ammount
+        // The shift amount is negated such that a shift amount
         // of 1 (in 64-bit) is encoded as 0b111111 and a shift
         // amount of 64 is encoded as 0b000000,
         // in the bottom 6 bits.

cranelift/codegen/src/isa/aarch64/inst/mod.rs

@@ -158,7 +158,7 @@ fn inst_size_test() {
 }
 
 impl Inst {
-    /// Create an instruction that loads a constant, using one of serveral options (MOVZ, MOVN,
+    /// Create an instruction that loads a constant, using one of several options (MOVZ, MOVN,
     /// logical immediate, or constant pool).
     pub fn load_constant<F: FnMut(Type) -> Writable<Reg>>(
         rd: Writable<Reg>,

cranelift/codegen/src/isa/riscv64/inst.isle

@@ -726,7 +726,7 @@
   (CSexth)
 ))
 
-;; This is a mix of all Zcb memory adressing instructions
+;; This is a mix of all Zcb memory addressing instructions
 ;;
 ;; Technically they are split across 4 different formats.
 ;; But they are all very similar, so we just group them all together.
@@ -1130,7 +1130,7 @@
 (rule (rv_xor rs1 rs2)
   (alu_rrr (AluOPRRR.Xor) rs1 rs2))
 
-;; Helper for emitting the `xori` ("Exlusive Or Immediate") instruction.
+;; Helper for emitting the `xori` ("Exclusive Or Immediate") instruction.
 ;; rd ← rs1 ⊕ uext(imm)
 (decl rv_xori (XReg Imm12) XReg)
 (rule (rv_xori rs1 imm)
@@ -1172,13 +1172,13 @@
 (rule (rv_snez rs1)
   (rv_sltu (zero_reg) rs1))
 
-;; Helper for emiting the `slti` ("Set Less Than Immediate") instruction.
+;; Helper for emitting the `slti` ("Set Less Than Immediate") instruction.
 ;; rd ← rs1 < imm
 (decl rv_slti (XReg Imm12) XReg)
 (rule (rv_slti rs1 imm)
   (alu_rr_imm12 (AluOPRRI.Slti) rs1 imm))
 
-;; Helper for emiting the `sltiu` ("Set Less Than Immediate Unsigned") instruction.
+;; Helper for emitting the `sltiu` ("Set Less Than Immediate Unsigned") instruction.
 ;; rd ← rs1 < imm
 (decl rv_sltiu (XReg Imm12) XReg)
 (rule (rv_sltiu rs1 imm)
@@ -2092,7 +2092,7 @@
         dst))
 
 ;; some instruction use imm12 as funct12.
-;; so we don't need the imm12 paramter.
+;; so we don't need the imm12 parameter.
 (decl alu_rr_funct12 (AluOPRRI Reg) Reg)
 (rule (alu_rr_funct12 op src)
       (let ((dst WritableXReg (temp_writable_xreg))
@@ -2630,7 +2630,7 @@
         dst))
 
 ;;; some float binary operation
-;;; 1. need move into x reister.
+;;; 1. need move into x register.
 ;;; 2. do the operation.
 ;;; 3. move back.
 (decl lower_float_binary (AluOPRRR FReg FReg Type) FReg)
@@ -2863,7 +2863,7 @@
   (i128_sub (value_regs_zero) val))
 
 
-;; Builds an instruction sequence that traps if the comparision succeeds.
+;; Builds an instruction sequence that traps if the comparison succeeds.
 (decl gen_trapif (IntCC XReg XReg TrapCode) InstOutput)
 (rule (gen_trapif cc a b trap_code)
   (side_effect (SideEffectNoResult.Inst (MInst.TrapIf a b cc trap_code))))

cranelift/codegen/src/isa/riscv64/inst/emit.rs

@@ -855,7 +855,7 @@ impl Inst {
                 // Right now we only put a u32 or u64 in this instruction.
                 // It is not very long, no need to check if need `emit_island`.
                 // If data is very long , this is a bug because RawData is typecial
-                // use to load some data and rely on some positon in the code stream.
+                // use to load some data and rely on some position in the code stream.
                 // and we may exceed `Inst::worst_case_size`.
                 // for more information see https://github.com/bytecodealliance/wasmtime/pull/5612.
                 sink.put_data(&data[..]);
@@ -1867,7 +1867,7 @@ impl Inst {
                     //   auipc rd, 0              # R_RISCV_GOT_HI20 (symbol_name)
                     //   ld    rd, rd, 0          # R_RISCV_PCREL_LO12_I (label)
 
-                    // Create the lable that is going to be published to the final binary object.
+                    // Create the label that is going to be published to the final binary object.
                     let auipc_label = sink.get_label();
                     sink.bind_label(auipc_label, &mut state.ctrl_plane);
 
@@ -1938,7 +1938,7 @@ impl Inst {
                 //
                 // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#global-dynamic
 
-                // Create the lable that is going to be published to the final binary object.
+                // Create the label that is going to be published to the final binary object.
                 let auipc_label = sink.get_label();
                 sink.bind_label(auipc_label, &mut state.ctrl_plane);
 

cranelift/codegen/src/isa/riscv64/inst/encode.rs

@@ -415,7 +415,7 @@ pub fn encode_ci_sp_load(op: CiOp, rd: WritableReg, imm: Uimm6) -> u16 {
     // LDSP:  [5|4:3|8:6]
     // FLDSP: [5|4:3|8:6]
     //
-    // We don't recieve the entire offset in `imm`, just a multiple of the load-size.
+    // We don't receive the entire offset in `imm`, just a multiple of the load-size.
 
     // Number of bits in the lowest position of imm. 3 for lwsp, 2 for {f,}ldsp.
     let low_bits = match op {
@@ -509,7 +509,7 @@ pub fn encode_css_type(op: CssOp, src: Reg, imm: Uimm6) -> u16 {
     // c.sdsp:  [5:3|8:6]
     // c.fsdsp: [5:3|8:6]
     //
-    // We don't recieve the entire offset in `imm`, just a multiple of the load-size.
+    // We don't receive the entire offset in `imm`, just a multiple of the load-size.
 
     // Number of bits in the lowest position of imm. 4 for c.swsp, 3 for c.{f,}sdsp.
     let low_bits = match op {

cranelift/codegen/src/isa/riscv64/inst/imms.rs

@@ -62,7 +62,7 @@ impl Display for Imm12 {
     }
 }
 
-// singed
+// signed
 #[derive(Clone, Copy, Default)]
 pub struct Imm20 {
     /// 32-bit container where the low 20 bits are the data payload.

cranelift/codegen/src/isa/riscv64/inst_vector.isle

@@ -1017,7 +1017,7 @@
 (rule (rv_vfabs_v vs mask vstate) (rv_vfsgnjx_vv vs vs mask vstate))
 
 ;; Helper for emitting the `vfsqrt.v` instruction.
-;; This instruction splats the F regsiter into all elements of the destination vector.
+;; This instruction splats the F register into all elements of the destination vector.
 (decl rv_vfsqrt_v (VReg VecOpMasking VState) VReg)
 (rule (rv_vfsqrt_v vs mask vstate)
   (vec_alu_rr (VecAluOpRR.VfsqrtV) vs mask vstate))
@@ -1097,41 +1097,41 @@
 
 ;; Helper for emitting the `vmv.x.s` instruction.
 ;; This instruction copies the first element of the source vector to the destination X register.
-;; Masked versions of this instuction are not supported.
+;; Masked versions of this instruction are not supported.
 (decl rv_vmv_xs (VReg VState) XReg)
 (rule (rv_vmv_xs vs vstate)
   (vec_alu_rr (VecAluOpRR.VmvXS) vs (unmasked) vstate))
 
 ;; Helper for emitting the `vfmv.f.s` instruction.
 ;; This instruction copies the first element of the source vector to the destination F register.
-;; Masked versions of this instuction are not supported.
+;; Masked versions of this instruction are not supported.
 (decl rv_vfmv_fs (VReg VState) FReg)
 (rule (rv_vfmv_fs vs vstate)
   (vec_alu_rr (VecAluOpRR.VfmvFS) vs (unmasked) vstate))
 
 ;; Helper for emitting the `vmv.s.x` instruction.
 ;; This instruction copies the source X register into first element of the source vector.
-;; Masked versions of this instuction are not supported.
+;; Masked versions of this instruction are not supported.
 (decl rv_vmv_sx (XReg VState) VReg)
 (rule (rv_vmv_sx vs vstate)
   (vec_alu_rr (VecAluOpRR.VmvSX) vs (unmasked) vstate))
 
 ;; Helper for emitting the `vfmv.s.f` instruction.
 ;; This instruction copies the source F register into first element of the source vector.
-;; Masked versions of this instuction are not supported.
+;; Masked versions of this instruction are not supported.
 (decl rv_vfmv_sf (FReg VState) VReg)
 (rule (rv_vfmv_sf vs vstate)
   (vec_alu_rr (VecAluOpRR.VfmvSF) vs (unmasked) vstate))
 
 ;; Helper for emitting the `vmv.v.x` instruction.
-;; This instruction splats the X regsiter into all elements of the destination vector.
+;; This instruction splats the X register into all elements of the destination vector.
 ;; Masked versions of this instruction are called `vmerge`
 (decl rv_vmv_vx (XReg VState) VReg)
 (rule (rv_vmv_vx vs vstate)
   (vec_alu_rr (VecAluOpRR.VmvVX) vs (unmasked) vstate))
 
 ;; Helper for emitting the `vfmv.v.f` instruction.
-;; This instruction splats the F regsiter into all elements of the destination vector.
+;; This instruction splats the F register into all elements of the destination vector.
 ;; Masked versions of this instruction are called `vmerge`
 (decl rv_vfmv_vf (FReg VState) VReg)
 (rule (rv_vfmv_vf vs vstate)
@@ -1862,7 +1862,7 @@
     res))
 
 
-;; Retruns the maximum value integer value that can be represented by a float
+;; Returns the maximum value integer value that can be represented by a float
 (decl float_int_max (Type) u64)
 (rule (float_int_max $F32) 0x4B000000)
 (rule (float_int_max $F64) 0x4330000000000000)