VHDL Traffic lights

Implement, in VHDL, a digital system that, starting from the FPGA 100Mhz clock signal, handles the operation modes of a semaphore.

Digital Systems (Computer Science MSc) exam final project. Academic year 2017/2018.

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
ClockGenerator.vhd		ClockGenerator.vhd
Counter.vhd		Counter.vhd
FSM.vhd		FSM.vhd
LICENSE		LICENSE
Presentazione.pdf		Presentazione.pdf
Presentazione.pptx		Presentazione.pptx
README.md		README.md
SignalControlGenerator.vhd		SignalControlGenerator.vhd
TestBench.vhd		TestBench.vhd

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