PyTV 0.4.0

Bug Fixes

• Fix Python Indentation for Verilog Generation

Example:

module `OUTPUT_VERILOG_FILE_STEM`#(
    parameter dwt = 16
)(
    op_in, clk
//! if (if_rst):
    , rst_n
//! if (if_en):
    , en
//! #
    , op_out
);

This is part of the example D1.pytv, where //! # is required to get the correct indentation so that the Python syntax is correct in generation.

Notably, after a Python line ended with : (discarding comments, which is implemented as a regex :\s*(#|$) that is not very strict), the Verilog print indentation will automatically add one level.

Full Changelog: v0.3.3...v0.4.0