Add fast_if vs slow_if comparison

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>

xls/examples/BUILD

@@ -22,6 +22,7 @@ load(
     "//xls/build_rules:xls_build_defs.bzl",
     "cc_xls_ir_jit_wrapper",
     "xls_benchmark_ir",
+    "xls_benchmark_verilog",
     "xls_dslx_fmt_test",
     "xls_dslx_ir",
     "xls_dslx_library",
@@ -1023,3 +1024,142 @@ xls_dslx_test(
     srcs = ["gcd.x"],
     deps = [":gcd_dslx"],
 )
+
+### IF experiments ###
+
+xls_dslx_library(
+    name = "if_dslx",
+    srcs = [
+        "if.x",
+    ],
+)
+
+## Slow IF
+
+xls_dslx_verilog(
+    name = "slow_if_verilog",
+    codegen_args = {
+        "module_name": "slow_if",
+        "generator": "pipeline",
+        "delay_model": "asap7",
+        "pipeline_stages": "1",
+        "worst_case_throughput": "1",
+        "use_system_verilog": "false",
+    },
+    dslx_top = "slow_if_inst",
+    library = ":if_dslx",
+    verilog_file = "slow_if.v",
+)
+
+xls_benchmark_ir(
+    name = "slow_if_opt_ir_benchmark",
+    src = ":slow_if_verilog.opt.ir",
+    benchmark_ir_args = {
+        "pipeline_stages": "10",
+        "delay_model": "asap7",
+    },
+)
+
+verilog_library(
+    name = "slow_if_verilog_lib",
+    srcs = [
+        ":slow_if.v",
+    ],
+)
+
+synthesize_rtl(
+    name = "slow_if_asap7_synth",
+    standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt",
+    top_module = "slow_if",
+    deps = [
+        ":slow_if_verilog_lib",
+    ],
+)
+
+place_and_route(
+    name = "slow_if_place_and_route",
+    clock_period = "650",
+    core_padding_microns = 2,
+    die_height_microns = 500,
+    die_width_microns = 500,
+    min_pin_distance = "0.5",
+    placement_density = "0.30",
+    stop_after_step = "global_routing",
+    synthesized_rtl = ":slow_if_asap7_synth",
+    target_die_utilization_percentage = "10",
+)
+
+benchmark_synth(
+    name = "slow_if_asap7_synth_benchmark",
+    synth_target = ":slow_if_asap7_synth",
+)
+
+xls_benchmark_verilog(
+    name = "slow_if_verilog_benchmark",
+    verilog_target = "slow_if_verilog",
+)
+
+## Fast IF
+
+xls_dslx_verilog(
+    name = "fast_if_verilog",
+    codegen_args = {
+        "module_name": "fast_if",
+        "generator": "pipeline",
+        "delay_model": "asap7",
+        "pipeline_stages": "1",
+        "worst_case_throughput": "1",
+        "use_system_verilog": "false",
+    },
+    dslx_top = "fast_if_inst",
+    library = ":if_dslx",
+    verilog_file = "fast_if.v",
+)
+
+xls_benchmark_ir(
+    name = "fast_if_opt_ir_benchmark",
+    src = ":fast_if_verilog.opt.ir",
+    benchmark_ir_args = {
+        "pipeline_stages": "10",
+        "delay_model": "asap7",
+    },
+)
+
+verilog_library(
+    name = "fast_if_verilog_lib",
+    srcs = [
+        ":fast_if.v",
+    ],
+)
+
+synthesize_rtl(
+    name = "fast_if_asap7_synth",
+    standard_cells = "@org_theopenroadproject_asap7sc7p5t_28//:asap7-sc7p5t_rev28_rvt",
+    top_module = "fast_if",
+    deps = [
+        ":fast_if_verilog_lib",
+    ],
+)
+
+place_and_route(
+    name = "fast_if_place_and_route",
+    clock_period = "650",
+    core_padding_microns = 2,
+    die_height_microns = 500,
+    die_width_microns = 500,
+    min_pin_distance = "0.5",
+    placement_density = "0.30",
+    stop_after_step = "global_routing",
+    synthesized_rtl = ":fast_if_asap7_synth",
+    target_die_utilization_percentage = "10",
+)
+
+benchmark_synth(
+    name = "fast_if_asap7_synth_benchmark",
+    synth_target = ":fast_if_asap7_synth",
+)
+
+xls_benchmark_verilog(
+    name = "fast_if_verilog_benchmark",
+    verilog_target = "fast_if_verilog",
+)

xls/examples/if.x

@@ -0,0 +1,37 @@
+// Copyright 2022 The XLS Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+fn slow_if<N: u32>(cond: bool, arg1: uN[N], arg2: uN[N]) -> uN[N] {
+    if cond { arg1 } else { arg2 }
+}
+
+fn fast_if<N: u32>(cond: bool, arg1: uN[N], arg2: uN[N]) -> uN[N] {
+    let mask = if (cond) {!bits[N]:0} else {bits[N]:0};
+    (arg1 & mask) | (arg2 & !mask)
+}
+
+#[test]
+fn fast_if_test() {
+    assert_eq(if  true { u32:1 } else { u32:5 }, fast_if(true,  u32:1, u32:5));
+    assert_eq(if false { u32:1 } else { u32:5 }, fast_if(false, u32:1, u32:5));
+}
+
+fn slow_if_inst(cond: bool, arg1: uN[1024], arg2: uN[1024]) -> uN[1024] {
+    slow_if<u32:1024>(cond, arg1, arg2)
+}
+
+fn fast_if_inst(cond: bool, arg1: uN[1024], arg2: uN[1024]) -> uN[1024] {
+    fast_if<u32:1024>(cond, arg1, arg2)
+}