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aarch64: Add special-case for widening multiplication
This commit adds a special case to the lowering of 128-bit multiplication on the aarch64 backend along the same lines as was done in bytecodealliance#9136 for the x64 backend. Notably zero and sign-extended values which are multiplied to produce a 128-bit result can skip some of the arithmetic of the fully general 128-bit lowering.
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Original file line number | Diff line number | Diff line change |
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test compile precise-output | ||
set enable_llvm_abi_extensions=true | ||
target aarch64 | ||
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function %mul_uextend_i64(i64, i64) -> i128 { | ||
block0(v0: i64, v1: i64): | ||
v2 = uextend.i128 v0 | ||
v3 = uextend.i128 v1 | ||
v4 = imul v2, v3 | ||
return v4 | ||
} | ||
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||
; VCode: | ||
; block0: | ||
; madd x3, x0, x1, xzr | ||
; umulh x1, x0, x1 | ||
; mov x0, x3 | ||
; ret | ||
; | ||
; Disassembled: | ||
; block0: ; offset 0x0 | ||
; mul x3, x0, x1 | ||
; umulh x1, x0, x1 | ||
; mov x0, x3 | ||
; ret | ||
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||
function %mul_sextend_i64(i64, i64) -> i128 { | ||
block0(v0: i64, v1: i64): | ||
v2 = sextend.i128 v0 | ||
v3 = sextend.i128 v1 | ||
v4 = imul v2, v3 | ||
return v4 | ||
} | ||
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||
; VCode: | ||
; block0: | ||
; madd x3, x0, x1, xzr | ||
; smulh x1, x0, x1 | ||
; mov x0, x3 | ||
; ret | ||
; | ||
; Disassembled: | ||
; block0: ; offset 0x0 | ||
; mul x3, x0, x1 | ||
; smulh x1, x0, x1 | ||
; mov x0, x3 | ||
; ret | ||
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