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A 12 Hour Digital Clock Implemented on Nexys4 DDR FPGA board using Verilog HDL.

GPL-3.0 license

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LICENSE		LICENSE
README.md		README.md
project schematic.png		project schematic.png
project_report.pdf		project_report.pdf

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Digitalclock12Hr

A 12 Hour Digital Clock Implemented on Nexys4 DDR FPGA board using Verilog HDL.

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A 12 Hour Digital Clock Implemented on Nexys4 DDR FPGA board using Verilog HDL.

fpga projects verilog hdl vlsi digital-clock nexys4ddr 12-hour-clock

GPL-3.0 license

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