update mhint4 to enhance performance when L2 miss with ACE bus

XUANTIE-RV · Jun 19, 2024 · 3458846 · 3458846
1 parent 77ceaed
commit 3458846
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/feature.c b/feature.c
@@ -109,7 +109,7 @@ void setup_features(void)
 			csr_write(CSR_MHINT, 0x31ea32c);
 			csr_write(CSR_MHINT2, 0x180);
 			csr_write(CSR_MHCR, 0x11ff);
-			csr_write(CSR_MHINT4, 0x80);
+			csr_write(CSR_MHINT4, 0x2080);
 #if __riscv_xlen == 64
 			csr_write(CSR_MENVCFG, 0x4000000000000000);
 #endif
@@ -161,7 +161,7 @@ void setup_features(void)
 			csr_write(CSR_MHINT4, 0x10000080);
 #if __riscv_xlen == 64
 			csr_write(CSR_MENVCFG, 0x4000000000000000);
-#endif	
+#endif
 		} else {
 			while(1);
 		}