Added burst write axi

VUnit · Jun 12, 2024 · 947388e · 947388e
1 parent 1f53450
commit 947388e
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Showing 3 changed files with 26 additions and 12 deletions.
diff --git a/vunit/vhdl/verification_components/src/axi_master.vhd b/vunit/vhdl/verification_components/src/axi_master.vhd
@@ -238,31 +238,33 @@ begin
           size := get_full_write_size;
           burst := axi_burst_type_fixed;
           id(id'range) := (others => '0');
+          resp :=  axi_resp_okay;
         elsif msg_type = bus_burst_write_msg then
           byteenable(byteenable'range) := (others => '1'); -- not set in bus master pkg
           len := pop_integer(request_msg) - 1; -- bring bus burst down to axi zero based indexing
           data := pop_std_ulogic_vector(request_msg);
           size := get_full_write_size;
           burst := axi_burst_type_incr;
           id(id'range) := (others => '0');
+          resp :=  axi_resp_okay;
         elsif msg_type = axi_write_msg then 
           data := pop_std_ulogic_vector(request_msg);
           byteenable := pop_std_ulogic_vector(request_msg);
           len := 0;
           size := pop_std_ulogic_vector(request_msg);
           burst := axi_burst_type_fixed;
           id := pop_std_ulogic_vector(request_msg)(arid'length -1 downto 0);
+          resp := pop_std_ulogic_vector(request_msg);
         elsif msg_type = axi_burst_write_msg then 
-          data := pop_std_ulogic_vector(request_msg);
           byteenable := pop_std_ulogic_vector(request_msg);
           len := to_integer(unsigned(pop_std_ulogic_vector(request_msg)));
           size := pop_std_ulogic_vector(request_msg);
           burst := pop_std_ulogic_vector(request_msg);
           id := pop_std_ulogic_vector(request_msg)(arid'length -1 downto 0);
+          resp := pop_std_ulogic_vector(request_msg);
+          data := pop_std_ulogic_vector(request_msg);
         end if;
 
-        resp := pop_std_ulogic_vector(request_msg) when is_axi_msg(msg_type) else axi_resp_okay;
-
         w_done := false;
         aw_done := false;
 

diff --git a/vunit/vhdl/verification_components/src/axi_master_pkg.vhd b/vunit/vhdl/verification_components/src/axi_master_pkg.vhd
@@ -39,11 +39,10 @@ package axi_master_pkg is
   procedure burst_write_axi(signal net : inout network_t;
                           constant bus_handle : bus_master_t;
                           constant address : std_logic_vector;
-                          constant data : std_logic_vector;
                           constant len : std_logic_vector;
                           constant size : std_logic_vector;
                           constant burst : axi_burst_type_t;
-                          constant last : std_logic;
+                          constant data : queue_t;
                           constant id : std_logic_vector := "";
                           constant expected_bresp : axi_resp_t := axi_resp_okay;
                           -- default byte enable is all bytes
@@ -169,11 +168,10 @@ package body axi_master_pkg is
   procedure burst_write_axi(signal net : inout network_t;
                            constant bus_handle : bus_master_t;
                            constant address : std_logic_vector;
-                           constant data : std_logic_vector;
                            constant len : std_logic_vector;
                            constant size : std_logic_vector;
                            constant burst : axi_burst_type_t;
-                           constant last : std_logic;
+                           constant data : queue_t;
                            constant id : std_logic_vector := "";
                            constant expected_bresp : axi_resp_t := axi_resp_okay;
                            -- default byte enable is all bytes
@@ -189,9 +187,6 @@ package body axi_master_pkg is
     full_address(address'length - 1 downto 0) := address;
     push_std_ulogic_vector(request_msg, full_address);
 
-    full_data(data'length - 1 downto 0) := data;
-    push_std_ulogic_vector(request_msg, full_data);
-
     if byte_enable = "" then
       full_byte_enable := (others => '1');
     else
@@ -214,9 +209,13 @@ package body axi_master_pkg is
     end if;
     push_std_ulogic_vector(request_msg, full_id);
 
-    push_std_ulogic(request_msg, last);
-
     push_std_ulogic_vector(request_msg, expected_bresp);
+
+    for i in 0 to to_integer(unsigned(len)) loop
+      full_data(bus_handle.p_data_length-1 downto 0) := pop(data);
+      push_std_ulogic_vector(request_msg, full_data);
+    end loop;
+
     send(net, bus_handle.p_actor, request_msg);
   end procedure;
 

diff --git a/vunit/vhdl/verification_components/test/tb_axi_master.vhd b/vunit/vhdl/verification_components/test/tb_axi_master.vhd
@@ -242,6 +242,19 @@ begin
         check_true(is_empty(memory_data_queue), "memory_data_queue not flushed");
         wait_on_data_write_memory(memory);
       end loop;
+
+    elsif run("Test random burstcount write with burst_write_axi") then
+        for n in 0 to 4 loop
+          info(tb_logger, "Setup...");
+          burst := rnd.RandInt(1, 255);
+          setup_and_set_random_data_write_memory(memory, burst+1, wdata'length, memory_data_queue);
+          info(tb_logger, "Reading...");
+          burst_write_axi(net, bus_handle, x"00000000", std_logic_vector(to_unsigned(burst, awlen'length)),"001", axi_burst_type_incr, memory_data_queue, x"25", axi_resp_okay);
+          info(tb_logger, "Compare...");
+          check_true(is_empty(memory_data_queue), "memory_data_queue not flushed");
+          wait_on_data_write_memory(memory);
+        end loop;
+
     end if;
 
     wait for 100 ns;