Fix UART receiver

According to stnolting#890
[bug] uart issue after stnolting#883 upd

The change is in neorv32_uart.vhd file
In 289 line:
From rx_engine.sreg(8 downto 1) to rx_engine.sreg(7 downto 0)

rtl/core/neorv32_uart.vhd

@@ -286,7 +286,7 @@ begin
   );
 
   rx_fifo.clear <= '1' when (ctrl.enable = '0') or (ctrl.sim_mode = '1') else '0';
-  rx_fifo.wdata <= rx_engine.sreg(8 downto 1);
+  rx_fifo.wdata <= rx_engine.sreg(7 downto 0);
   rx_fifo.we    <= rx_engine.done;
   rx_fifo.re    <= '1' when (bus_req_i.stb = '1') and (bus_req_i.rw = '0') and (bus_req_i.addr(2) = '1') else '0';