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Make the files consistently formatted #1
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This is how the formatting would look like with current verible; some look better, some worse. A lot of files could not be processed, possibly due to some large initializer lists (a known issue with verible) Also one crash on CC: @fangism |
Yes, I see a number of bugs that amount to unhandled cases in the formatter's view of the syntax tree. We haven't tested it much on library-style verilog yet, but this makes for a nice sample set. |
A few logfiles * [process.log](./process.log): exit code. 67 files parsed and formatted, 181 files created at least one syntax error, and 2 files resulted in a segfault. * [syntaxerrors.log](./syntaxerrors.log) output of syntax errors. * [unique-syntaxerrors.log](./unique-syntaxerrors.log) : set of unique syntaxerrors, with count. Explorations for SymbiFlow#1
Did another round of formatting: findings: 181 files out of 250 have some sort of parse error. Funny: the Xilinx ascii-art, with a backslash at the end of a comment prompts verible to indent: |
Here is a breakdown of syntax errors seen. I suspect a lot of these are due to preprocessing weirdness.
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@hzeller - A lot of those sound like the "specify" stuff which Yosys also doesn't like. |
Current status: formatted files in https://github.com/hzeller/XilinxUnisimLibrary/tree/formatting-experience3 branch (this commit ) 165 files parse, 85 still fail (vs. 69 parse and 181 failure last time. Progress). Unique syntax errors:
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I think a lot of errors also come from limited preprocessing by Verible and subsequent confusion. |
New run. Some formatting changes since last time (typically looks better): 145 files parse, 81 fail, and 24 crash formatting (b/169742626). Crashes are regression from last time:
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Most notable changes:
if/else are more compact:
became
often this is better, sometimes not necessarily when the Concatenation operators became worse: (verilog/src/unisims/DSP_ALU.v) assign comux_w = ((smux & {comux4simd[46:0], 1'b0}) |
(wmux & {comux4simd[46:0], 1'b0}) |
(smux & wmux)); became: assign comux_w = ((smux & {
comux4simd[46:0], 1'b0
}) | (wmux & {
comux4simd[46:0], 1'b0
}) | (smux & wmux)); |
Acknowledged.
Acknowledged. If you have time, issues with reduced test cases would be helpful. |
Maybe we can use google/verible for this?
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