This release can be used to replicate the experimental results for the FPGA emulation vs. CPU simulation comparison, for the case that ADC slices and PI slices are modeled individually in emulation (i.e., using a detailed event system on the FPGA). A future release will model analog_core as a single block for emulation, comparison purposes. Note that the ZC706 experimental results were gathered with anasymod v0.3.2 (not v0.2.9 as in the setup.py file). (The regression test passed without this update because the regression server uses ZC702 boards).