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Shreesh-Kulkarni/README.md

Hi 👋, I'm Shreesh Kulkarni, a passionate RISC-V Microarchitecture Researcher

I'm currently working with OpenHW Group, RISC-V International and The Linux Foundation on the CORE-V Wally Project. Our team aims to bring Wally to TRL-5 and improve overall performance of the RISC-V CPU.

image

  • 🌱 I’m currently learning RISC-V,SystemVerilog,Digital Design(Verilog HDL) and Formal Verification

  • 👯 I’m looking to collaborate on Microchip PICs,FPGAs,RISC-V,Embedded Programming and Computer Architecture projects

  • 📫 How to reach me kshreesh5@gmail.com or my college email - shreeshkulkarni.201ee155@nitk.edu.in

You can connect with me on LinkedIn, or view my resume - here.

👨‍💻 Languages

🔧 Tools

pycharm Gnu Octave Arduino Xilinx

shreesh-kulkarni

 shreesh-kulkarni

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  1. cvw cvw Public

    Forked from openhwgroup/cvw

    CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

    Assembly

  2. RISC-V-Core RISC-V-Core Public

    A repository consisting of all the project files and codes for RISC-V Processor design using Transaction Level Verilog.

    SystemVerilog 5

  3. rvc-tlv rvc-tlv Public

    Repository for implementing the C-extension decoder/decompressor for RV32I.

    TL-Verilog

  4. formal-verif formal-verif Public

    A repository for formal verification using Yosys.

    SMT 1

  5. warp-v warp-v Public

    Forked from stevehoover/warp-v

    WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

    TL-Verilog

  6. Hardware-Modelling-Verilog Hardware-Modelling-Verilog Public

    All basic to advanced hardware models which are used in VLSI Frontend Design using Verilog HDL

    Verilog 1