A high level design for a tensor processing ASIC.
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The Goal of this project is to develop the design of an ASIC for processing Deep Learning Tensors with high efficiency.
The primary end goal is the creation of a reference design, including the interface and ops that is completely open source.
Contact for explanation of conditions.
Currently, a high level design for the basic processing unit has been created.
This document goes over a basic evaluation of the standard implementation of a Systolic Array such as the ones used in Google's TPU.
The VSA Unit is the core variation from existing architectures like a Standard Systolic Array.
This is the primary goal of this project, but is only just in the initial stages.
The current license is AGPL, more details on that choice.
Once the Primary goal of creating a full open-source Reference design is completed, the license will be changed to CC0/Public Domain.
NO contract, NDA, Trade Secret, or other legal agreement may restrict information or actions directly related to this project (Except where Required by Law).
This project and any derivative projects may not be dual licensed, or have their license made less restrictive except with relation to the conditions above.
You can see the list of items that need more help here.
By contributing, you explicitly agree to the CC0/Public Domain condition of this project's License, and agree to release your contributions when the full project is relicensed.