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1. digital_lab digital_lab Public

   Laboratory works for digital electronics course in Kyiv Polytechnic Institute, Department of Design of Electronic Digital Equipment, Electronics faculty

   Verilog 29 15

2. Netmaker_vc_router_syn_quartus Netmaker_vc_router_syn_quartus Public

   Router for Network-on-Chip (NoC) with Virtual Channels (VC) from Netmaker library, modified for synthesis in Quartus II

   Verilog 6 4

3. LAG_sv_sim_predef_traffic_predef_links LAG_sv_sim_predef_traffic_predef_links Public

   Synthesizable Network-on-Chip (NoC) with Link Aggregation (LAG), written in System Verilog. Allows to define spatial distribution of traffic for a given application and choose number of physical li…

   Verilog 4

4. dsp_sdr_basic dsp_sdr_basic Public

   Python 4

5. LAG_sv_sim_random_traffic LAG_sv_sim_random_traffic Public

   Synthesizable Network-on-Chip (NoC) with Link Aggregation (LAG), written in System Verilog. Implements uniform-random spatial distribution of traffic and equal number of physical links in each trun…

   Verilog 3

6. LAG_sv_syn_quartus LAG_sv_syn_quartus Public

   Network-on-Chip (NoC) with Link Aggregation (LAG), modified for synthesis in Quartus II. Repo contains LAG.tcl that creates and configures Quartus II project of the NoC with LAG. In addition, gate …

   Verilog 2