TODO's regarding BaseBoard:
- Schematics:
- DDR3 for PL (72-bit ECC) could be implemented with a standart 204-pin SODIM connector in order to reduce stackup cost by using a Module.
- Change Non-Volatile Memory from NOR QSPI to a MRAM for better radiation hardness.
- Adapt DaughterBoard interface to comply with SYZYGY TXR-4 tranceiver peripheral specification.
- Documentation:
- Add Outputjob file similar to this.
TODO's regarding DaughterBoard:
- Schematics:
- Select and add ADC.
- Power tree!
- Route:
- RF required changes detected after simulation.