Do cleanup for the FPGA-accelerated pow #63
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Here is a summary for cleaning implementation of the FPGA-accelerated pow up * Do not have a responsibility to multi-thread management as possible * Do not implememt multi-threads * Clean up fpga registers map, e.g. tick count and hach count
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Is it possible that 2 more FPGA boards on the one platform in the future? At this time, you will need |
src/pow_fpga_accel.c
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| close(devmem_fd); | ||
| free(ctx); | ||
| } | ||
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| static void *PoWFPGAAccel_getPoWContext(ImplContext *impl_ctx, | ||
| int8_t *trytes, | ||
| int mwm) | ||
| { | ||
| pthread_mutex_lock(&impl_ctx->lock); |
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Actually, this statement also can be dropped if you ensure that only 1 fpga board would be supported on the platform. Or it should be reserved for extensibility as well as PoWFPGAAccel_freePoWContext.
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Yes, I agree your point. I will drop this lock.
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I think one dcurl maps one FPGA board. |
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@ajblane Please note that in the README and I would approve this PR. |
docs/FPGA-ACCEL.md
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| For IOTA FPGA-accelerated integration into dcurl, we consider one dcurl maps one FPGA board unlike the GPU-accelerated solution which is considered a multi-GPU scenario. | ||
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| Here is a simple summary of integrating FPGA-accelerated solution into dcurl: | ||
| * Do not have a responsibility to multi-thread management as possible |
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"Only one thread is allowed to do FPGA PoW"
docs/FPGA-ACCEL.md
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| Here is a simple summary of integrating FPGA-accelerated solution into dcurl: | ||
| * Do not have a responsibility to multi-thread management as possible | ||
| * Do not implememt multi-threads |
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"No multi-thread management inside the FPGA Implementation Context is implemented"
Here is a summary for cleaning implementation of the FPGA-accelerated
pow up