Designinig a Pipelined in-order 5 stage RISC-V core RV32I-MF
- a working linux termimnal (WSL, ubuntu, Etc...).
- python3 or higher installed follow this link
- RISC-V GCC toolchain installed follow this link
- Intel ModelSim simulator installed follow this link
git clone https://github.com/ChrisShakkour/RV32I-MAF-project.git
cd RV32I-MAF-project
source source_me.sh
compile_hdl -top CoreTop_TB
how to use compile_hdl
compile_gcc -src <some c source file> -elf -txt -mem
how to use compile_gcc
simulate -test <test name>
how to use simulate
git clone https://github.com/ChrisShakkour/RV32I-MAF-project.git
cd RV32I-MAF-project
source source_me.sh
compile_hdl -top CoreTop_TB
compile_gcc -src verif/tests/TowerOfHanoi/TowerOfHanoi.c -elf -txt -mem
simulate -test TowerOfHanoi