Add support for menvcgf and mseccfg CSRs

This commit adds basic support for menvcgf and mseccfg, note that they change
execution behavior for modes above M so there is nothing special to do to
emulate those.

Cargo.toml

@@ -18,6 +18,7 @@ members = [
     "payloads/csr_id",
     "payloads/pmp",
     "payloads/perf_monitor",
+    "payloads/menv_msec",
 
     # Crates
     "crates/mirage_abi",

justfile

@@ -18,7 +18,8 @@ test:
 	cargo run --package runner -- --payload csr_id
 	cargo run --package runner -- --payload pmp
 	cargo run --package runner -- --payload perf_monitor
-
+	cargo run --package runner -- --payload menv_msec
+
 	# Checking formatting...
 	cargo fmt --all -- --check
 

payloads/menv_msec/Cargo.toml

@@ -0,0 +1,7 @@
+[package]
+name = "menv_msec"
+version = "0.1.0"
+edition = "2021"
+
+[dependencies]
+mirage_abi = { path = "../../crates/mirage_abi" }

payloads/menv_msec/src/main.rs

@@ -0,0 +1,58 @@
+#![no_std]
+#![no_main]
+
+use core::arch::{asm, global_asm};
+use core::panic::PanicInfo;
+use core::usize;
+
+use mirage_abi::{failure, success};
+
+global_asm!(
+    r#"
+.text
+.align 4
+.global _start
+_start:
+    j {entry}
+"#,
+    entry = sym entry,
+);
+
+extern "C" fn entry() -> ! {
+    let secret: usize = 0x42;
+    let mut res: usize;
+    unsafe {
+        asm!(
+            "li {0}, 0x42",
+            "csrw menvcfg, {0}",
+            "csrr {1}, menvcfg",
+            in(reg) secret,
+            out(reg) res,
+        );
+    }
+
+    read_test(res, secret);
+
+    unsafe {
+        asm!(
+            "li {0}, 0x42",
+            "csrw mseccfg, {0}",
+            "csrr {1}, mseccfg",
+            in(reg) secret,
+            out(reg) res,
+        );
+    }
+
+    read_test(res, secret);
+
+    success()
+}
+
+fn read_test(out_csr: usize, expected: usize) {
+    assert_eq!(out_csr, expected);
+}
+
+#[panic_handler]
+fn panic(_info: &PanicInfo) -> ! {
+    failure();
+}

src/arch/registers.rs

@@ -84,6 +84,10 @@ pub enum Csr {
     Mhpmevent(usize),
     /// Machine counter enable
     Mcounteren,
+    /// Machine environment configuration register
+    Menvcgf,
+    /// Machine security configuration register
+    Mseccfg,
     /// An unknown CSR
     Unknown,
 }

src/decoder.rs

@@ -143,6 +143,8 @@ fn decode_csr(csr: usize) -> Csr {
         0x320 => Csr::Mcountinhibit,
         0x323..=0x33F => Csr::Mhpmevent(csr - 0x323),
         0x306 => Csr::Mcounteren,
+        0x30a => Csr::Menvcgf,
+        0x747 => Csr::Mseccfg,
         _ => {
             log::info!("Unknown CSR: 0x{:x}", csr);
             Csr::Unknown

src/virt.rs

@@ -61,6 +61,8 @@ pub struct VirtCsr {
     mcountinhibit: usize,
     mhpmevent: [usize; 29],
     mcounteren: usize,
+    menvcfg: usize,
+    mseccfg: usize,
 }
 
 impl Default for VirtCsr {
@@ -82,6 +84,8 @@ impl Default for VirtCsr {
             mcountinhibit: 0,
             mhpmevent: [0; 29],
             mcounteren: 0,
+            menvcfg: 0,
+            mseccfg: 0,
         }
     }
 }
@@ -146,6 +150,8 @@ impl RegisterContext<Csr> for VirtContext {
             Csr::Mcountinhibit => self.csr.mcountinhibit,
             Csr::Mhpmevent(n) => self.csr.mhpmevent[n],
             Csr::Mcounteren => self.csr.mcounteren,
+            Csr::Menvcgf => self.csr.menvcfg,
+            Csr::Mseccfg => self.csr.mseccfg,
             Csr::Unknown => panic!("Tried to access unknown CSR: {:?}", register),
         }
     }
@@ -203,6 +209,8 @@ impl RegisterContext<Csr> for VirtContext {
             Csr::Mcountinhibit => (),             // Read-only 0
             Csr::Mhpmevent(_event_idx) => (),     // Read-only 0
             Csr::Mcounteren => (),                // Read-only 0
+            Csr::Menvcgf => self.csr.menvcfg = value,
+            Csr::Mseccfg => self.csr.mseccfg = value,
             Csr::Unknown => panic!("Tried to access unknown CSR: {:?}", register),
         }
     }