Skip to content
View Akul-Verma's full-sized avatar
Block or Report

Block or report Akul-Verma

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. Verification-of-UART-communication-protocol-design-using-System-Verilog Verification-of-UART-communication-protocol-design-using-System-Verilog Public

  2. Vending-Machine-FPGA-SYNTHESISABLE Vending-Machine-FPGA-SYNTHESISABLE Public

    This is a classic example of how to apply theoretical knowlegde to some practical application .In this project I have made a vending machine by implementing it's state diagram as a Verilog code and…

  3. Voting-Machine-FPGA-SYNTHESISABLE- Voting-Machine-FPGA-SYNTHESISABLE- Public

  4. Banking-System-Cpp-OOPS Banking-System-Cpp-OOPS Public

  5. generating-VHDL-and-Verilog-code-for-full-adder-using-MATLAB-HDL-coder generating-VHDL-and-Verilog-code-for-full-adder-using-MATLAB-HDL-coder Public

  6. -Verifying-4-bit-Multiplier-design-using-System-Verilog -Verifying-4-bit-Multiplier-design-using-System-Verilog Public