Skip to content
View AkshayXPatil's full-sized avatar
🎯
Focusing
🎯
Focusing

Block or report AkshayXPatil

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. Design-verification Design-verification Public

    UVM and Systemverilog based test benches for functional verification of a RAM module

    SystemVerilog 6 5

  2. FM-partioner FM-partioner Public

    Fiduccia-Mattheyses method to bi-partition the ISPD 2016 benchmarks and minimized the cutset

    C++ 5 4

  3. Standard-cell-placement-engine Standard-cell-placement-engine Public

    Simulated Annealing based fixed-die standard cell placement engine for IBM benchmark netlists

    C++ 5 5

  4. MSDAP MSDAP Public

    Complete design of a Mini Stereo Digital Audio Processor

    Verilog 3 4

  5. Physical-Layout-Design Physical-Layout-Design Public

    Complete design of USART interface with baud rate selection

    Verilog 2 2